Home
last modified time | relevance | path

Searched refs:u32_t (Results 1 – 25 of 96) sorted by relevance

1234

/titanic_41/usr/src/uts/common/io/bnxe/577xx/hsi/mcp/
H A Dncsi_basic_types.h81 typedef u32_t* pu32_t;
183 u32_t High;
184 u32_t Low;
192 u32_t IsEnabled;
237 u32_t EgressPktsDroppedNoSaMatch;
238 u32_t IngressPktsDroppedVlanMis;
239 u32_t CmdsDroppedSizeErr;
240 u32_t CmdsDroppedChanPkgIdErr;
241 u32_t CmdsDroppedNcsiHdrRevErr;
249 u32_t LandMark;
[all …]
H A Dmcp_fio.h46 u32_t mcpf_events_bits;
78 u32_t mcpf_attentions_bits;
87 u32_t mcpf_event_enable;
88 u32_t mcpf_attention_enable;
89 u32_t mcpf_fio_status;
93 u32_t mcpf_interrupt_status;
103 u32_t mcpf_unused_a[2];
104 u32_t mcpf_unused_b[8];
105 u32_t mcpf_mcp_hc_inc_stat[8];
106 u32_t mcpf_unused_c[4];
[all …]
H A Dncsi_cmds.h165 u32_t Reserved1[2];
219 u32_t Reserved1[2];
247 u32_t OperationType;
257 u32_t Address;
258 u32_t WordCount;
262 u32_t Address;
263 u32_t WordCount;
264 u32_t Value;
335 u32_t Reserved;
346 u32_t Reserved;
[all …]
H A Dnvm_map.h62 u32_t magic_value; /* a pattern not likely to occur randomly */
64 u32_t sram_start_addr; /* where to locate boot code (byte addr) */
66 u32_t code_len; /* boot code length (in dwords) */
67 u32_t code_start_addr; /* location of code on media (media byte addr) */
68 u32_t crc; /* 32-bit CRC */
88 u32_t sram_start_addr; /* Relative to the execution CPU, see code image
90 u32_t code_attribute;
180 u32_t nvm_start_addr;
196 u32_t unused[5]; /* Must be all zeroes */
199 u32_t crc;
[all …]
/titanic_41/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/l4/include/
H A Dlm_l4st.h21 u32_t current_offset_in_pattern_buf[MAX_PATTERN_IDX];
22 u32_t skip_bytes_in_incoming_buf[MAX_PATTERN_IDX];
23 u32_t is_offsets_initialized;
30 u32_t pattern_buf_size;
31 u32_t pattern_size;
48 u32_t size;
51 u32_t more_to_comp;
53 u32_t flags; /* Flags for indicating the start and end of an io buffer. */
68 u32_t app_buf_size; /* Number of bytes of all buffers from BUFFER_START till BUFFER_END */
69 …u32_t app_buf_xferred; /* Number of bytes xferred on all buffers from BUFFER_START till BUFFER_EN…
[all …]
/titanic_41/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/include/
H A Dcommon_uif.h252 u32_t overwrite_settings;
253 u32_t msg_tx_hold;
254 u32_t msg_fast_tx;
255 u32_t tx_credit_max;
256 u32_t msg_tx_interval;
257 u32_t tx_fast;
265 u32_t ver_num;
269 u32_t _reserved[50];
270 u32_t admin_status;
275 u32_t remote_chassis_id[65];
[all …]
H A Dlm.h115 u32_t size; /* Mask size */
116 u32_t pattern_size; /* Pattern size */
119 u32_t crc32 ; // crc32 on (pattern & mask)
130 u32_t cnt;
136 typedef u32_t lm_interrupt_status_t;
224 IN const u32_t idx);
248 struct _lm_device_t *pdev, u32_t cid);
372 IN const u32_t func_mailbox_num,
373 OUT u32_t* fw_port_stats_ptr,
374 OUT u32_t* fw_func_stats_ptr );
[all …]
H A Dlm_stats.h124 void lm_stats_fw_assign ( struct _lm_device_t* pdev, IN u32_t stats_flags_done, OUT u32_t* p…
127 void lm_pf_stats_vf_fw_assign(struct _lm_device_t *pdev, u32_t stats_flags_done, u32_t* ptr_…
131 void lm_stats_fw_check_update_done( struct _lm_device_t *pdev, OUT u32_t* ptr_stats_flags_do…
293 u32_t rx_stat_ifhcinoctets ;
294 u32_t rx_stat_ifhcinbadoctets ;
295 u32_t rx_stat_etherstatsfragments ;
296 u32_t rx_stat_ifhcinucastpkts ;
297 u32_t rx_stat_ifhcinmulticastpkts ;
298 u32_t rx_stat_ifhcinbroadcastpkts ;
299 u32_t rx_stat_dot3statsfcserrors ;
[all …]
H A Dlm5710.h179 u32_t kuku = 0xcafecafe; \
224 u32_t cid;
464 #define OFFSETOF(_s, _m) ((u32_t) PTR_SUB(&((_s *) 0)->_m, (u8_t *) 0))
483 u32_t upper_align_power_of_2(IN const u16_t num, IN const u8_t num_bits_supported);
535 u32_t aborted;
547 u32_t buf_size;
553 u32_t mtu;
554 u32_t lah_size;
555 u32_t num_rx_desc;
556 u32_t num_tx_desc;
[all …]
/titanic_41/usr/src/uts/common/io/bnxe/577xx/include/
H A Dl4states.h114 u32_t host_reachability_delta;
120 u32_t nic_reachability_delta;
141 u32_t dst_ip;
142 u32_t src_ip;
147 u32_t dst_ip[4];
148 u32_t src_ip[4];
156 u32_t path_mtu;
188 u32_t hash_value;
203 u32_t initial_rcv_wnd;
208 u32_t rcv_indication_size;
[all …]
H A Dlm_defs.h69 #define SIG(_p) (*((u32_t *) ((u8_t *) (_p) - sizeof(u32_t))))
70 #define END_SIG(_p, _size) (*((u32_t *) ((u8_t *) (_p) + (_size))))
133 typedef u32_t lm_rx_mask_t;
150 typedef u32_t lm_flow_control_t;
183 typedef u32_t lm_medium_t;
261 u32_t flag;
270 u32_t _reserved;
293 typedef u32_t lm_offload_t;
320 typedef u32_t lm_rss_hash_t;
354 typedef u32_t lm_wake_up_mode_t;
[all …]
/titanic_41/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/fw/
H A D5710_hsi.h9 u32_t attn_bits /* 16 bit of attention signal lines */;
10 u32_t attn_bits_ack /* 16 bit of attention signal ack */;
14 u32_t reserved1 /* resreved for padding */;
23 u32_t __reserved0[10];
32 u32_t agg_vars1;
78 u32_t rel_seq /* The sequence to release */;
79 u32_t rel_seq_th /* The threshold for the released sequence */;
105 u32_t __cq_u_prod1 /* Ustorm producer of CQ 1 */;
128 u32_t __agg_vars1 /* Various aggregative variables*/;
138 u32_t rel_seq /* The sequence to release */;
[all …]
/titanic_41/usr/src/uts/common/io/bnxe/
H A Dbnxe.h228 u32_t fw_ver;
230 u32_t mtu[LM_CLI_IDX_MAX];
232 u32_t routeTxRingPolicy;
233 u32_t numRings; /* number of rings */
234 u32_t numRxDesc[LM_CLI_IDX_MAX]; /* number of RX descriptors */
235 u32_t numTxDesc[LM_CLI_IDX_MAX]; /* number of TX descriptors */
236 u32_t maxRxFree; /* max free allowed before posting back */
237 u32_t maxTxFree; /* max free allowed before posting back */
240 u32_t intrRxPerSec;
241 u32_t intrTxPerSec;
[all …]
H A Dbnxe_mm_l4.c177 u32_t mm_tcp_rx_indicate_gen_buf ( in mm_tcp_rx_indicate_gen_buf()
213 u32_t mm_tcp_get_gen_bufs( in mm_tcp_get_gen_bufs()
216 u32_t nbufs, in mm_tcp_get_gen_bufs()
228 u32_t flags, in mm_tcp_return_gen_bufs()
239 u32_t flags, in mm_tcp_return_list_of_gen_bufs()
247 u32_t mm_tcp_copy_to_tcp_buf( in mm_tcp_copy_to_tcp_buf()
252 u32_t tcp_buf_offset, in mm_tcp_copy_to_tcp_buf()
253 u32_t nbytes in mm_tcp_copy_to_tcp_buf()
273 u32_t new_mss, in mm_tcp_update_required_gen_bufs()
274 u32_t old_mss, in mm_tcp_update_required_gen_bufs()
[all …]
/titanic_41/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/
H A Dcontext.h16 void * lm_get_context(struct _lm_device_t *pdev, u32_t cid);
19 u64_t lm_get_context_phys(struct _lm_device_t *pdev, u32_t cid);
27 u32_t src_ip[4]; /* in host order */
28 u32_t dst_ip[4]; /* in host order */
41 lm_status_t lm_allocate_cid(struct _lm_device_t *pdev, u32_t type, void * cookie, s32_t * cid);
60 void lm_free_cid(struct _lm_device_t *pdev, u32_t type, u32_t cid, u8_t notify_fw);
66 lm_status_t lm_searcher_mirror_hash_insert(struct _lm_device_t *pdev, u32_t cid, lm_4tuple_t *tuple…
71 void lm_searcher_mirror_hash_remove(struct _lm_device_t *pdev, u32_t cid);
76 void * lm_cid_cookie(struct _lm_device_t *pdev, u32_t type, u32_t cid);
81 lm_cid_resc_t * lm_cid_resc(struct _lm_device_t *pdev, u32_t cid);
[all …]
H A Dlm_util.c48 u32_t count_bits(u32_t n) in count_bits()
109 u32_t LOG2(u32_t v){ in LOG2()
110 u32_t r=0; in LOG2()
129 u32_t
133 u32_t const largest_power_of_2 = 1 << (num_bits_supported - 1); in upper_align_power_of_2()
134 u32_t prev_power_of_2 = largest_power_of_2; in upper_align_power_of_2()
135 u32_t cur_power_of_2 = 0; in upper_align_power_of_2()
184 u32_t val = 0; in lm_chip_is_slow()
198 lm_status_t lm_wait_state_change(struct _lm_device_t *pdev, volatile u32_t * curr_state, u32_t new_… in lm_wait_state_change()
200 u32_t delay_us = 0; in lm_wait_state_change()
[all …]
H A Dlm_mcp.c79 OUT u32_t * magic_val in lm_clp_reset_prep()
82 u32_t val = 0; in lm_clp_reset_prep()
83 u32_t offset; in lm_clp_reset_prep()
87 ASSERT_STATIC(sizeof(struct mf_cfg) % sizeof(u32_t) == 0); in lm_clp_reset_prep()
104 IN u32_t magic_val in lm_clp_reset_done()
107 u32_t val = 0; in lm_clp_reset_done()
108 u32_t offset; in lm_clp_reset_done()
133 lm_status_t lm_reset_mcp_prep(lm_device_t *pdev, u32_t * magic_val) in lm_reset_mcp_prep()
135 u32_t shmem; in lm_reset_mcp_prep()
136 u32_t validity_offset; in lm_reset_mcp_prep()
[all …]
H A Dlm_hw_access.c59 void lm_cmng_init(struct _lm_device_t *pdev, u32_t port_rate) in lm_cmng_init()
62 u32_t i = 0; in lm_cmng_init()
63 u32_t* buf = NULL; in lm_cmng_init()
120 buf = (u32_t *)&ram_data.vnic.vnic_max_rate[vnic]; in lm_cmng_init()
144 buf = (u32_t *)&ram_data.port.rs_vars; in lm_cmng_init()
152 buf = (u32_t *)&ram_data.port.fair_vars; in lm_cmng_init()
160 buf = (u32_t *)&ram_data.port.flags; in lm_cmng_init()
172 buf = (u32_t *)&ram_data.vnic.vnic_min_rate[vnic]; in lm_cmng_init()
339 u32_t val = 0; in lm_setup_fan_failure_detection()
410 lm_status_t lm_gpio_read(struct _lm_device_t *pdev, u32_t pin_num, u32_t* value_ptr, u8_t port) in lm_gpio_read()
[all …]
H A Dlm_nvram.c55 u32_t j, cnt; in acquire_nvram_lock()
56 u32_t val; in acquire_nvram_lock()
107 u32_t j, cnt; in release_nvram_lock()
108 u32_t val; in release_nvram_lock()
147 u32_t val, j, cnt;
194 u32_t cnt,j,val;
234 u32_t val; in enable_nvram_access()
256 u32_t val; in disable_nvram_access()
278 u32_t offset, in nvram_read_dword()
279 u32_t *ret_val, in nvram_read_dword()
[all …]
H A Dlm_power.c46 u32_t
52 u32_t nwuf_cnt = 0 ; in init_nwuf_57710()
53 u32_t offset = 0 ; in init_nwuf_57710()
55 u32_t val = 0 ; in init_nwuf_57710()
57 u32_t val_32[2] = {0} ; in init_nwuf_57710()
58 u32_t mod = 0 ; in init_nwuf_57710()
59 u32_t idx = 0 ; in init_nwuf_57710()
60 u32_t bit = 0 ; in init_nwuf_57710()
61 u32_t reg_len = 0 ; in init_nwuf_57710()
62 u32_t reg_crc = 0 ; in init_nwuf_57710()
[all …]
H A Dlm_er.c85 u32_t val; in lm_er_disable_close_the_gate()
101 u32_t val, enable_bit; in lm_er_set_234_gates()
147 u32_t not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2; in lm_er_process_kill_chip_reset()
215 u32_t cnt = 1000; in lm_er_empty_tetris_buffer()
216 u32_t sr_cnt = 0; in lm_er_empty_tetris_buffer()
217 u32_t blk_cnt = 0; in lm_er_empty_tetris_buffer()
218 u32_t port_is_idle_0 = 0; in lm_er_empty_tetris_buffer()
219 u32_t port_is_idle_1 = 0; in lm_er_empty_tetris_buffer()
220 u32_t pgl_exp_rom2 = 0; in lm_er_empty_tetris_buffer()
221 u32_t pgl_b_reg_tags = 0; in lm_er_empty_tetris_buffer()
[all …]
/titanic_41/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/
H A Ddbg_bus.h9 u32_t addr;
10 u32_t value;
17 u32_t count;
32 u32_t dbg_block_on;
33 u32_t intr_buffer_read_ptr;
34 u32_t intr_buffer_wr_ptr;
35 u32_t ext_buffer_wr_ptr_lsb;
36 u32_t ext_buffer_wr_ptr_msb;
37 u32_t dbg_ovl_on_ext_buffer;
38 u32_t dbg_wrap_ext;
[all …]
/titanic_41/usr/src/uts/common/io/bnxe/577xx/drivers/common/include/
H A Dmm_linux.h184 u32_t *bar_sz);
191 u32_t * bar_sz
197 u32_t offset,
205 u32_t offset,
212 u32_t offset,
213 u32_t * ret
220 u32_t offset,
228 u32_t offset,
236 u32_t offset,
244 u32_t offset,
[all …]
H A Dmm_uefi.h39 typedef u32_t mm_int_ptr_t;
50 static __inline void mm_atomic_set_imp(u32_t *p, u32_t v) in mm_atomic_set_imp()
57 static __inline s32_t mm_atomic_dec_imp(u32_t *p) in mm_atomic_dec_imp()
66 static __inline s32_t mm_atomic_inc_imp(u32_t *p) in mm_atomic_inc_imp()
75 static __inline s32_t mm_atomic_and_imp(u32_t *p, u32_t v) in mm_atomic_and_imp()
96 static __inline s32_t mm_atomic_or_imp(u32_t *p, u32_t v) in mm_atomic_or_imp()
120 static __inline s32_t mm_atomic_cmpxchg_imp(u32_t *p, in mm_atomic_cmpxchg_imp()
121 u32_t old_v, in mm_atomic_cmpxchg_imp()
122 u32_t new_v) in mm_atomic_cmpxchg_imp()
137 …LM_BAR_WR32_OFFSET((PDEV), BAR_1, (u32_t)((int_ptr_t)((u8_t *)(PDEV)->context_info->array[CID].cid…
[all …]
H A Dmm.h212 u32_t delay_us);
216 u32_t pci_reg,
217 u32_t *reg_value);
221 u32_t pci_reg,
222 u32_t reg_value);
231 u32_t size,
238 u32_t mm_desc_size(struct _lm_device_t *pdev,
239 u32_t desc_type);
257 u32_t offset,
258 u32_t size,
[all …]

1234