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Searched refs:writeq_relaxed (Results 1 – 25 of 39) sorted by relevance

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/linux/drivers/net/ethernet/cavium/thunder/
H A Dthunder_xcv.c72 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
77 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
87 writeq_relaxed(cfg, xcv->reg_base + XCV_DLL_CTL); in xcv_init_hw()
94 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
102 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
106 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
130 writeq_relaxed(cfg, xcv->reg_base + XCV_CTL); in xcv_setup_link()
135 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_setup_link()
140 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_setup_link()
143 writeq_relaxed(0x01, xcv->reg_base + XCV_BATCH_CRD_RET); in xcv_setup_link()
[all …]
H A Dnic_main.c90 writeq_relaxed(val, nic->reg_base + offset); in nic_reg_write()
146 writeq_relaxed(msg[0], mbx_addr); in nic_send_msg_to_vf()
147 writeq_relaxed(msg[1], mbx_addr + 8); in nic_send_msg_to_vf()
149 writeq_relaxed(msg[1], mbx_addr + 8); in nic_send_msg_to_vf()
150 writeq_relaxed(msg[0], mbx_addr); in nic_send_msg_to_vf()
/linux/drivers/perf/
H A Dfujitsu_uncore_pmu.c77 writeq_relaxed(0, uncorepmu->regs + PM_EVCNTR(idx)); in fujitsu_uncore_counter_start()
80 writeq_relaxed(PM_EVTYPE_EVSEL(event->attr.config), uncorepmu->regs + PM_EVTYPE(idx)); in fujitsu_uncore_counter_start()
83 writeq_relaxed(PM_INTENSET_IDX(idx), uncorepmu->regs + PM_INTENSET); in fujitsu_uncore_counter_start()
86 writeq_relaxed(PM_CNTCTL_RESET, uncorepmu->regs + PM_CNTCTL(idx)); in fujitsu_uncore_counter_start()
87 writeq_relaxed(PM_CNTENSET_IDX(idx), uncorepmu->regs + PM_CNTENSET); in fujitsu_uncore_counter_start()
96 writeq_relaxed(PM_CNTENCLR_IDX(idx), uncorepmu->regs + PM_CNTENCLR); in fujitsu_uncore_counter_stop()
99 writeq_relaxed(PM_INTENCLR_IDX(idx), uncorepmu->regs + PM_INTENCLR); in fujitsu_uncore_counter_stop()
120 writeq_relaxed(PM_CR_RESET, uncorepmu->regs + PM_CR); in fujitsu_uncore_init()
122 writeq_relaxed(PM_CNTENCLR_RESET, uncorepmu->regs + PM_CNTENCLR); in fujitsu_uncore_init()
123 writeq_relaxed(PM_INTENCLR_RESET, uncorepmu->regs + PM_INTENCLR); in fujitsu_uncore_init()
[all …]
H A Darm_smmuv3_pmu.c734 writeq_relaxed(doorbell, pmu->reg_base + SMMU_PMCG_IRQ_CFG0); in smmu_pmu_write_msi_msg()
746 writeq_relaxed(0, pmu->reg_base + SMMU_PMCG_IRQ_CFG0); in smmu_pmu_setup_msi()
785 writeq_relaxed(counter_present_mask, in smmu_pmu_reset()
787 writeq_relaxed(counter_present_mask, in smmu_pmu_reset()
789 writeq_relaxed(counter_present_mask, in smmu_pmu_reset()
H A Darm-cmn.c1471 writeq_relaxed(CMN_CC_INIT, pmccntr); in arm_cmn_read_cc()
1558 writeq_relaxed(le64_to_cpu(dn->event_sel_w), dn->pmu_base + CMN_PMU_EVENT_SEL); in arm_cmn_set_event_sel_lo()
1578 writeq_relaxed(CMN_CC_INIT, CMN_DT_PMCCNTR(dtc)); in arm_cmn_event_start()
1588 writeq_relaxed(val, base + CMN_DTM_WPn_VAL(wp_idx)); in arm_cmn_event_start()
1589 writeq_relaxed(mask, base + CMN_DTM_WPn_MASK(wp_idx)); in arm_cmn_event_start()
1617 writeq_relaxed(0, base + CMN_DTM_WPn_MASK(wp_idx)); in arm_cmn_event_stop()
1618 writeq_relaxed(~0ULL, base + CMN_DTM_WPn_VAL(wp_idx)); in arm_cmn_event_stop()
1957 writeq_relaxed(reg, dtm->base + CMN_DTM_PMU_CONFIG); in arm_cmn_event_add()
2123 writeq_relaxed(dtm->pmu_config_low, dtm->base + CMN_DTM_PMU_CONFIG); in arm_cmn_init_dtm()
2126 writeq_relaxed(0, dtm->base + CMN_DTM_WPn_MASK(i)); in arm_cmn_init_dtm()
[all …]
/linux/drivers/iommu/arm/arm-smmu/
H A Darm-smmu-qcom-debug.c213 writeq_relaxed(val, tbu->base + DEBUG_SID_HALT_REG); in qcom_tbu_trigger_atos()
214 writeq_relaxed(iova, tbu->base + DEBUG_VA_ADDR_REG); in qcom_tbu_trigger_atos()
216 writeq_relaxed(val, tbu->base + DEBUG_AXUSER_REG); in qcom_tbu_trigger_atos()
228 writeq_relaxed(val, tbu->base + DEBUG_TXN_TRIGG_REG); in qcom_tbu_trigger_atos()
254 writeq_relaxed(0, tbu->base + DEBUG_TXN_TRIGG_REG); in qcom_tbu_trigger_atos()
255 writeq_relaxed(0, tbu->base + DEBUG_VA_ADDR_REG); in qcom_tbu_trigger_atos()
H A Darm-smmu-nvidia.c93 writeq_relaxed(val, reg); in nvidia_smmu_write_reg64()
/linux/include/linux/
H A Dio-64-nonatomic-lo-hi.h54 #ifndef writeq_relaxed
55 #define writeq_relaxed lo_hi_writeq_relaxed macro
H A Dio-64-nonatomic-hi-lo.h54 #ifndef writeq_relaxed
55 #define writeq_relaxed hi_lo_writeq_relaxed macro
H A Dcoresight.h559 writeq_relaxed(val, csa->base + offset); in csdev_access_relaxed_write64()
/linux/arch/mips/loongson64/
H A Dsmp.c143 writeq_relaxed(0, ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x0); in legacy_ipi_clear_buf()
159 writeq_relaxed(startargs[3], in legacy_ipi_write_buf()
161 writeq_relaxed(startargs[2], in legacy_ipi_write_buf()
163 writeq_relaxed(startargs[1], in legacy_ipi_write_buf()
165 writeq_relaxed(startargs[0], in legacy_ipi_write_buf()
/linux/arch/arm64/kernel/
H A Dsmp_spin_table.c92 writeq_relaxed(pa_holding_pen, release_addr); in smp_spin_table_cpu_prepare()
H A Dacpi_parking_protocol.c102 writeq_relaxed(__pa_symbol(secondary_entry), in acpi_parking_protocol_cpu_boot()
/linux/tools/testing/selftests/kvm/include/arm64/
H A Dprocessor.h239 #define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c))) macro
244 #define writeq(v,c) ({ __iowmb(); writeq_relaxed((v),(c));})
/linux/rust/helpers/
H A Dio.c105 writeq_relaxed(value, addr); in rust_helper_writeq_relaxed()
/linux/drivers/soc/apple/
H A Dmailbox.c156 writeq_relaxed(msg.msg0, mbox->regs + mbox->hw->a2i_send0); in apple_mbox_send()
157 writeq_relaxed(FIELD_PREP(APPLE_MBOX_MSG1_MSG, msg.msg1), in apple_mbox_send()
/linux/tools/testing/selftests/kvm/lib/arm64/
H A Dgic_v3.c439 writeq_relaxed(val, rdist_base + GICR_PROPBASER); in gic_rdist_enable_lpis()
444 writeq_relaxed(val, rdist_base + GICR_PENDBASER); in gic_rdist_enable_lpis()
H A Dgic_v3_its.c27 writeq_relaxed(val, GITS_BASE_GVA + offset); in its_write_u64()
/linux/drivers/crypto/marvell/octeontx2/
H A Dotx2_cpt_common.h134 writeq_relaxed(val, reg_base + in otx2_cpt_write64()
/linux/rust/kernel/
H A Dio.rs289 writeq_relaxed <- u64
/linux/arch/riscv/include/asm/
H A Dmmio.h125 #define writeq_relaxed(v, c) ({ __io_rbw(); writeq_cpu((v), (c)); __io_raw(); }) macro
/linux/drivers/iommu/arm/arm-smmu-v3/
H A Dtegra241-cmdqv.c461 writeq_relaxed(0, REG_VCMDQ_PAGE1(vcmdq, BASE)); in tegra241_vcmdq_hw_deinit()
462 writeq_relaxed(0, REG_VCMDQ_PAGE1(vcmdq, CONS_INDX_BASE)); in tegra241_vcmdq_hw_deinit()
485 writeq_relaxed(vcmdq->cmdq.q.q_base, REG_VCMDQ_PAGE1(vcmdq, BASE)); in tegra241_vcmdq_hw_init()
1082 writeq_relaxed(vcmdq->cmdq.q.q_base, REG_VCMDQ_PAGE1(vcmdq, BASE)); in tegra241_vcmdq_hw_init_user()
H A Darm-smmu-v3.c3951 writeq_relaxed(doorbell, smmu->base + cfg[0]); in arm_smmu_write_msi_msg()
3962 writeq_relaxed(0, smmu->base + ARM_SMMU_GERROR_IRQ_CFG0); in arm_smmu_setup_msis()
3963 writeq_relaxed(0, smmu->base + ARM_SMMU_EVTQ_IRQ_CFG0); in arm_smmu_setup_msis()
3966 writeq_relaxed(0, smmu->base + ARM_SMMU_PRIQ_IRQ_CFG0); in arm_smmu_setup_msis()
4110 writeq_relaxed((dma & STRTAB_BASE_ADDR_MASK) | STRTAB_BASE_RA, in arm_smmu_write_strtab()
4153 writeq_relaxed(smmu->cmdq.q.q_base, smmu->base + ARM_SMMU_CMDQ_BASE); in arm_smmu_device_reset()
4179 writeq_relaxed(smmu->evtq.q.q_base, smmu->base + ARM_SMMU_EVTQ_BASE); in arm_smmu_device_reset()
4193 writeq_relaxed(smmu->priq.q.q_base, in arm_smmu_device_reset()
/linux/drivers/cpufreq/
H A Dapple-soc-cpufreq.c196 writeq_relaxed(reg, priv->reg_base + APPLE_DVFS_CMD); in apple_soc_cpufreq_set_target()
/linux/drivers/irqchip/
H A Dirq-ti-sci-inta.c466 writeq_relaxed(BIT(event_desc->vint_bit), in ti_sci_inta_manage_event()

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