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Searched refs:wb_info (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.c998 struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0]; in dcn20_populate_dml_writeback_from_context() local
1004 pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0; in dcn20_populate_dml_writeback_from_context()
1006 pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height; in dcn20_populate_dml_writeback_from_context()
1007 pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width; in dcn20_populate_dml_writeback_from_context()
1008 pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width; in dcn20_populate_dml_writeback_from_context()
1009 pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height; in dcn20_populate_dml_writeback_from_context()
1012 pipes[pipe_cnt].dout.wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c; in dcn20_populate_dml_writeback_from_context()
1013 pipes[pipe_cnt].dout.wb.wb_vtaps_chroma = wb_info->dwb_params.scaler_taps.v_taps_c; in dcn20_populate_dml_writeback_from_context()
1016 if (wb_info->dwb_params.out_format == dwb_scaler_mode_yuv420) { in dcn20_populate_dml_writeback_from_context()
1017 if (wb_info->dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC) in dcn20_populate_dml_writeback_from_context()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/
H A Ddml2_translation_helper.c1240 const struct dc_writeback_info *wb_info = &in->writeback_info[i]; in populate_dml_writeback_cfg_from_stream_state() local
1242 if (wb_info->wb_enabled) { in populate_dml_writeback_cfg_from_stream_state()
1243 out->WritebackEnable[location] = wb_info->wb_enabled; in populate_dml_writeback_cfg_from_stream_state()
1244 out->ActiveWritebacksPerSurface[location] = wb_info->dwb_params.cnv_params.src_width; in populate_dml_writeback_cfg_from_stream_state()
1245 out->WritebackDestinationWidth[location] = wb_info->dwb_params.dest_width; in populate_dml_writeback_cfg_from_stream_state()
1246 out->WritebackDestinationHeight[location] = wb_info->dwb_params.dest_height; in populate_dml_writeback_cfg_from_stream_state()
1248 out->WritebackSourceWidth[location] = wb_info->dwb_params.cnv_params.crop_en ? in populate_dml_writeback_cfg_from_stream_state()
1249 wb_info->dwb_params.cnv_params.crop_width : in populate_dml_writeback_cfg_from_stream_state()
1250 wb_info->dwb_params.cnv_params.src_width; in populate_dml_writeback_cfg_from_stream_state()
1252 out->WritebackSourceHeight[location] = wb_info->dwb_params.cnv_params.crop_en ? in populate_dml_writeback_cfg_from_stream_state()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_stream.c553 struct dc_writeback_info *wb_info) in dc_stream_add_writeback() argument
564 if (wb_info == NULL) { in dc_stream_add_writeback()
569 if (wb_info->dwb_pipe_inst >= MAX_DWB_PIPES) { in dc_stream_add_writeback()
576 wb_info->dwb_params.out_transfer_func = &stream->out_transfer_func; in dc_stream_add_writeback()
578 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
586 stream->writeback_info[i].dwb_pipe_inst == wb_info->dwb_pipe_inst) { in dc_stream_add_writeback()
587 stream->writeback_info[i] = *wb_info; in dc_stream_add_writeback()
594 stream->writeback_info[stream->num_wb_info++] = *wb_info; in dc_stream_add_writeback()
599 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
611 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.c3144 struct dc_writeback_info *wb_info = (struct dc_writeback_info *)&stream->writeback_info[i_wb]; in dcn401_program_all_writeback_pipes_in_tree_sequence() local
3147 if (wb_info->wb_enabled) { in dcn401_program_all_writeback_pipes_in_tree_sequence()
3155 if (pipe_ctx->plane_state == wb_info->writeback_source_plane) { in dcn401_program_all_writeback_pipes_in_tree_sequence()
3165 dcn401_disable_writeback_sequence(dc, wb_info, seq_state); in dcn401_program_all_writeback_pipes_in_tree_sequence()
3169 ASSERT(wb_info->dwb_pipe_inst < dc->res_pool->res_cap->num_dwb); in dcn401_program_all_writeback_pipes_in_tree_sequence()
3170 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dcn401_program_all_writeback_pipes_in_tree_sequence()
3174 dcn401_update_writeback_sequence(dc, wb_info, context, seq_state); in dcn401_program_all_writeback_pipes_in_tree_sequence()
3177 dcn401_enable_writeback_sequence(dc, wb_info, context, mpcc_inst, seq_state); in dcn401_program_all_writeback_pipes_in_tree_sequence()
3181 dcn401_disable_writeback_sequence(dc, wb_info, seq_state); in dcn401_program_all_writeback_pipes_in_tree_sequence()
3188 struct dc_writeback_info *wb_info, in dcn401_enable_writeback_sequence() argument
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/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm.c10691 struct dc_writeback_info *wb_info; in dm_set_writeback() local
10696 wb_info = kzalloc_obj(*wb_info); in dm_set_writeback()
10697 if (!wb_info) { in dm_set_writeback()
10705 kfree(wb_info); in dm_set_writeback()
10712 kfree(wb_info); in dm_set_writeback()
10724 wb_info->wb_enabled = true; in dm_set_writeback()
10726 wb_info->dwb_pipe_inst = 0; in dm_set_writeback()
10727 wb_info->dwb_params.dwbscl_black_color = 0; in dm_set_writeback()
10728 wb_info->dwb_params.hdr_mult = 0x1F000; in dm_set_writeback()
10729 wb_info->dwb_params.csc_params.gamut_adjust_type = CM_GAMUT_ADJUST_TYPE_BYPASS; in dm_set_writeback()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
H A Ddcn20_hwseq.h116 struct dc_writeback_info *wb_info,
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_stream.h479 struct dc_writeback_info *wb_info);