Searched refs:update_m_n (Results 1 – 5 of 5) sorted by relevance
266 crtc_state->update_m_n = false; in intel_crtc_duplicate_state()
948 (new_crtc_state->update_m_n || new_crtc_state->update_lrr || in intel_crtc_vrr_enabling()965 (new_crtc_state->update_m_n || new_crtc_state->update_lrr || in intel_crtc_vrr_disabling()1017 (new_crtc_state->update_lrr || new_crtc_state->update_m_n)); in intel_crtc_lobf_enabling()1028 (new_crtc_state->update_lrr || new_crtc_state->update_m_n)); in intel_crtc_lobf_disabling()5306 if (!fastset || !pipe_config->update_m_n) in intel_pipe_config_compare()5412 if (!fastset || !pipe_config->update_m_n) { in intel_pipe_config_compare()5610 crtc_state->update_m_n = false; in intel_crtc_flag_modeset()5831 new_crtc_state->update_m_n = false; in intel_crtc_check_fastset()6673 if (new_crtc_state->update_m_n) in intel_pipe_fastset()6863 new_crtc_state->update_m_n || new_crtc_state->update_lrr) in intel_update_crtc()
1060 bool update_m_n; /* update M/N seamlessly during fastset? */ member
3132 new_crtc_state->update_m_n || in intel_psr_pre_plane_update()
3283 pipe_config->update_m_n = true; in intel_dp_drrs_compute_config()