/linux/drivers/ufs/core/ |
H A D | ufshcd-crypto.c | 29 ufshcd_writel(hba, 0, slot_offset + 16 * sizeof(cfg->reg_val[0])); in ufshcd_program_key() 31 ufshcd_writel(hba, le32_to_cpu(cfg->reg_val[i]), in ufshcd_program_key() 35 ufshcd_writel(hba, le32_to_cpu(cfg->reg_val[17]), in ufshcd_program_key() 38 ufshcd_writel(hba, le32_to_cpu(cfg->reg_val[16]), in ufshcd_program_key()
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H A D | ufs-mcq.c | 98 ufshcd_writel(hba, val, REG_UFS_MCQ_CFG); in ufshcd_mcq_config_mac() 435 ufshcd_writel(hba, ufshcd_readl(hba, REG_UFS_MEM_CFG) | 0x2, in ufshcd_mcq_enable_esi() 442 ufshcd_writel(hba, msg->address_lo, REG_UFS_ESILBA); in ufshcd_mcq_config_esi() 443 ufshcd_writel(hba, msg->address_hi, REG_UFS_ESIUBA); in ufshcd_mcq_config_esi()
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H A D | ufshcd.c | 839 ufshcd_writel(hba, ~mask, REG_UTP_TRANSFER_REQ_LIST_CLEAR); in ufshcd_utrl_clear() 850 ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR); in ufshcd_utmrl_clear() 852 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR); in ufshcd_utmrl_clear() 926 ufshcd_writel(hba, INT_AGGR_ENABLE | in ufshcd_reset_intr_aggr() 940 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE | in ufshcd_config_intr_aggr() 952 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); in ufshcd_disable_intr_aggr() 963 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT, in ufshcd_enable_run_stop_reg() 965 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT, in ufshcd_enable_run_stop_reg() 980 ufshcd_writel(hba, val, REG_CONTROLLER_ENABLE); in ufshcd_hba_start() 2301 ufshcd_writel(hba, 1 << lrbp->task_tag, in ufshcd_send_command() [all …]
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/linux/drivers/ufs/host/ |
H A D | ufs-mediatek.c | 257 ufshcd_writel(hba, 0, in ufs_mtk_hce_enable_notify() 267 ufshcd_writel(hba, in ufs_mtk_hce_enable_notify() 326 ufshcd_writel(hba, REFCLK_REQUEST, REG_UFS_REFCLK_CTRL); in ufs_mtk_setup_ref_clk() 329 ufshcd_writel(hba, REFCLK_RELEASE, REG_UFS_REFCLK_CTRL); in ufs_mtk_setup_ref_clk() 381 ufshcd_writel(hba, 0x820820, REG_UFS_DEBUG_SEL); in ufs_mtk_dbg_sel() 382 ufshcd_writel(hba, 0x0, REG_UFS_DEBUG_SEL_B0); in ufs_mtk_dbg_sel() 383 ufshcd_writel(hba, 0x55555555, REG_UFS_DEBUG_SEL_B1); in ufs_mtk_dbg_sel() 384 ufshcd_writel(hba, 0xaaaaaaaa, REG_UFS_DEBUG_SEL_B2); in ufs_mtk_dbg_sel() 385 ufshcd_writel(hba, 0xffffffff, REG_UFS_DEBUG_SEL_B3); in ufs_mtk_dbg_sel() 387 ufshcd_writel(hba, 0x20, REG_UFS_DEBUG_SEL); in ufs_mtk_dbg_sel() [all …]
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H A D | ufs-sprd.c | 59 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE); in ufs_sprd_ctrl_uic_compl() 188 ufshcd_writel(hba, 0, REG_AUTO_HIBERNATE_IDLE_TIMER); in ufs_sprd_suspend() 232 ufshcd_writel(hba, val, REG_CONTROLLER_ENABLE); in ufs_sprd_n6_key_acc_enable()
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H A D | cdns-pltfrm.c | 134 ufshcd_writel(hba, core_clk_div, CDNS_UFS_REG_HCLKDIV); in cdns_ufs_set_hclkdiv() 242 ufshcd_writel(hba, data, CDNS_UFS_REG_PHY_XCFGD1); in cdns_ufs_m31_16nm_phy_initialization()
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H A D | ufs-renesas.c | 292 ufshcd_writel(hba, save[p->index], p->reg); in ufs_renesas_reg_control() 316 ufshcd_writel(hba, p->u.val, p->reg); in ufs_renesas_reg_control()
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H A D | ufshcd-dwc.c | 44 ufshcd_writel(hba, divider_val, DWC_UFS_REG_HCLKDIV); in ufshcd_dwc_program_clk_div()
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H A D | ufs-hisi.c | 232 ufshcd_writel(hba, UFS_HCLKDIV_NORMAL_VALUE, UFS_REG_HCLKDIV); in ufs_hisi_link_startup_pre_change() 237 ufshcd_writel(hba, reg, REG_AUTO_HIBERNATE_IDLE_TIMER); in ufs_hisi_link_startup_pre_change()
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H A D | ufshcd-pci.c | 108 ufshcd_writel(hba, hce, REG_CONTROLLER_ENABLE); in ufs_intel_hce_enable_notify()
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H A D | ufs-qcom.c | 559 ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US); in ufs_qcom_cfg_timers() 1560 ufshcd_writel(hba, reg, REG_UFS_CFG1); in ufs_qcom_dump_dbg_regs()
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H A D | ufs-exynos.c | 332 ufshcd_writel(hba, MH_MSG(enabled_vh, MH_MSG_PH_READY), PH2VH_MBOX); in exynosauto_ufs_post_pwr_change()
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/linux/include/ufs/ |
H A D | ufshcd.h | 1287 #define ufshcd_writel(hba, val, reg) \ macro 1306 ufshcd_writel(hba, tmp, reg); in ufshcd_rmwl()
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