Searched refs:uclk (Results 1 – 8 of 8) sorted by relevance
305 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz; in smu_v12_0_get_vbios_bootup_values()322 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz; in smu_v12_0_get_vbios_bootup_values()
539 for (i = 0; i < clk_table->uclk.num_clk_values; i++) { in dml2_core_utils_get_active_min_uclk_dpm_index()540 …L::%s: clk_table.uclk.clk_values_khz[%d] = %ld\n", __func__, i, clk_table->uclk.clk_values_khz[i]); in dml2_core_utils_get_active_min_uclk_dpm_index()542 if (uclk_freq_khz == clk_table->uclk.clk_values_khz[i]) { in dml2_core_utils_get_active_min_uclk_dpm_index()
930 clock_limit = smu->smu_table.boot_values.uclk; in smu_v15_0_0_get_dpm_ultimate_freq()1044 clock_limit = smu->smu_table.boot_values.uclk; in smu_v15_0_5_get_dpm_ultimate_freq()
586 VPD_ENTRY(uclk, 6); /* uP clk */671 ret = vpdstrtouint(vpd.uclk_data, vpd.uclk_len, 10, &p->uclk); in get_vpd_params()3364 t3_write_reg(adapter, A_CIM_HOST_ACC_DATA, vpd->uclk | fw_params); in t3_init_hw()
443 uint8_t uclk : 1; member
647 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; in smu_v13_0_7_set_default_dpm_table()
628 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; in smu_v13_0_0_set_default_dpm_table()
531 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; in smu_v14_0_2_set_default_dpm_table()