| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm_plane.c | 181 static void amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags(struct dc_tiling_info *tiling_info, in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags() argument
194 tiling_info->gfxversion = DcGfxVersion8; in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
196 tiling_info->gfx8.num_banks = num_banks; in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
197 tiling_info->gfx8.array_mode = in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
199 tiling_info->gfx8.tile_split = tile_split; in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
200 tiling_info->gfx8.bank_width = bankw; in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
201 tiling_info->gfx8.bank_height = bankh; in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
202 tiling_info->gfx8.tile_aspect = mtaspect; in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
203 tiling_info->gfx8.tile_mode = in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
207 tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1; in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
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| H A D | amdgpu_dm_plane.h | 50 struct dc_tiling_info *tiling_info,
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| H A D | amdgpu_dm.c | 6294 &plane_info->tiling_info, in fill_dc_plane_info_and_addr()
6343 dc_plane_state->tiling_info = plane_info.tiling_info; in fill_dc_plane_attributes()
8125 dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN; in dm_validate_stream_and_context()
8128 dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL; in dm_validate_stream_and_context()
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| /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn201/ |
| H A D | dcn201_hubp.c | 45 struct dc_tiling_info *tiling_info, in hubp201_program_surface_config() argument
53 hubp1_program_tiling(hubp, tiling_info, format); in hubp201_program_surface_config()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/ |
| H A D | dml21_utils.c | 305 memcpy(&phantom_plane->tiling_info, &main_plane->tiling_info, in dml21_add_phantom_plane()
306 sizeof(phantom_plane->tiling_info)); in dml21_add_phantom_plane()
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| H A D | dml21_translation_helper.c | 463 switch (plane_state->tiling_info.gfxversion) { in populate_dml21_surface_config_from_plane_state()
470 surface->tiling = gfx9_to_dml2_swizzle_mode(plane_state->tiling_info.gfx9.swizzle); in populate_dml21_surface_config_from_plane_state()
473 surface->tiling = gfx_addr3_to_dml2_swizzle_mode(plane_state->tiling_info.gfx_addr3.swizzle); in populate_dml21_surface_config_from_plane_state()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn10/ |
| H A D | dcn10_resource.c | 1260 plane_state->tiling_info.gfx9.swizzle = swizzle; in dcn10_patch_unknown_plane_state()
1312 void dcn10_get_default_tiling_info(struct dc_tiling_info *tiling_info) in dcn10_get_default_tiling_info() argument
1314 tiling_info->gfxversion = DcGfxVersion9; in dcn10_get_default_tiling_info()
1315 tiling_info->gfx9.swizzle = DC_SW_LINEAR; in dcn10_get_default_tiling_info()
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc.h | 1519 struct dc_tiling_info tiling_info; member
1592 struct dc_tiling_info tiling_info; member
1985 void dc_get_default_tiling_info(const struct dc *dc, struct dc_tiling_info *tiling_info);
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_hw_sequencer.c | 2041 struct dc_tiling_info *tiling_info = params->program_surface_config_params.tiling_info; in hwss_program_surface_config() local
2051 tiling_info, in hwss_program_surface_config()
2091 switch (bottom_pipe_ctx->plane_state->tiling_info.gfx9.swizzle) { in get_surface_tile_visual_confirm_color()
3917 struct dc_tiling_info *tiling_info, in hwss_add_hubp_program_surface_config() argument
3928 …state->steps[*seq_state->num_steps].params.program_surface_config_params.tiling_info = tiling_info; in hwss_add_hubp_program_surface_config()
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| H A D | dc_resource.c | 4450 pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) { in dc_validate_global_state()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource.c | 1700 memcpy(&phantom_plane->tiling_info, &curr_pipe->plane_state->tiling_info, in dcn32_enable_phantom_plane()
1701 sizeof(phantom_plane->tiling_info)); in dcn32_enable_phantom_plane()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/ |
| H A D | dce110_hwseq.c | 2346 if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL) in should_enable_fbc()
3069 &plane_state->tiling_info, in dce110_program_front_end_for_pipe()
3081 &plane_state->tiling_info, in dce110_program_front_end_for_pipe()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/ |
| H A D | dml2_translation_helper.c | 936 out->SurfaceTiling[location] = (enum dml_swizzle_mode)in->tiling_info.gfx9.swizzle; in populate_dml_surface_cfg_from_plane_state()
940 switch (in->tiling_info.gfx_addr3.swizzle) { in populate_dml_surface_cfg_from_plane_state()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| H A D | dcn20_resource.c | 2255 plane_state->tiling_info.gfx9.swizzle = DC_SW_64KB_S; in dcn20_patch_unknown_plane_state()
2257 plane_state->tiling_info.gfx9.swizzle = DC_SW_64KB_D; in dcn20_patch_unknown_plane_state()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | dcn20_fpu.c | 1687 swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle); in dcn20_populate_dml_pipes_from_context()
1688 swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle, in dcn20_populate_dml_pipes_from_context()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| H A D | dcn35_resource.c | 1794 plane_state->tiling_info.gfxversion = DcGfxVersion9; in dcn35_patch_unknown_plane_state()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 3668 plane_state->format, &plane_state->tiling_info, size, in dcn401_update_dchubp_dpp_sequence()
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