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Searched refs:state_array (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml2_0/
H A Ddml2_translation_helper.c363 p->in_states->state_array[0].socclk_mhz = 620.0; in dml2_init_soc_states()
364 p->in_states->state_array[0].dscclk_mhz = 716.667; in dml2_init_soc_states()
365 p->in_states->state_array[0].phyclk_mhz = 810; in dml2_init_soc_states()
366 p->in_states->state_array[0].phyclk_d18_mhz = 667; in dml2_init_soc_states()
367 p->in_states->state_array[0].phyclk_d32_mhz = 625; in dml2_init_soc_states()
368 p->in_states->state_array[0].dtbclk_mhz = 1564.0; in dml2_init_soc_states()
369 p->in_states->state_array[0].fabricclk_mhz = 450.0; in dml2_init_soc_states()
370 p->in_states->state_array[0].dcfclk_mhz = 300.0; in dml2_init_soc_states()
371 p->in_states->state_array[0].dispclk_mhz = 2150.0; in dml2_init_soc_states()
372 p->in_states->state_array[0].dppclk_mhz = 2150.0; in dml2_init_soc_states()
[all …]
H A Ddml2_wrapper_fpu.c195 …s->uclk_change_latencies[i] = dml2->v20.dml_core_ctx.states.state_array[i].dram_clock_change_laten… in calculate_lowest_supported_state_for_temp_read()
200 …dml2->v20.dml_core_ctx.states.state_array[j].dram_clock_change_latency_us = s_global->dummy_pstate… in calculate_lowest_supported_state_for_temp_read()
217 …while (dml2->v20.dml_core_ctx.states.state_array[result].dram_speed_mts < s_global->dummy_pstate_t… in calculate_lowest_supported_state_for_temp_read()
225 …dml2->v20.dml_core_ctx.states.state_array[i].dram_clock_change_latency_us = s->uclk_change_latenci… in calculate_lowest_supported_state_for_temp_read()
416 …out_clks.dcfclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dc… in dml2_validate_and_build_resource()
417 …out_clks.fclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].fabr… in dml2_validate_and_build_resource()
418 …out_clks.uclk_mts = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dram… in dml2_validate_and_build_resource()
419 …out_clks.phyclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].ph… in dml2_validate_and_build_resource()
420 …out_clks.socclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].so… in dml2_validate_and_build_resource()
421 …out_clks.ref_dtbclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx… in dml2_validate_and_build_resource()
[all …]
H A Ddml2_utils.c365 …context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = in_ctx->v20.dml_core_ctx.states.state_array[… in dml2_calculate_rq_and_dlg_params()
367 …context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = in_ctx->v20.dml_core_ctx.states.state_array in dml2_calculate_rq_and_dlg_params()
H A Ddisplay_mode_core_structs.h1268 …struct soc_state_bounding_box_st state_array[__DML_MAX_STATE_ARRAY_SIZE__]; /// <brief fixed size … member
H A Ddisplay_mode_core.c10071 return (states->state_array[state_idx]); in dml_get_soc_state_bounding_box()
/linux/drivers/gpu/drm/radeon/
H A Dtrinity_dpm.c1688 struct _StateArray *state_array; in trinity_parse_power_table() local
1703 state_array = (struct _StateArray *) in trinity_parse_power_table()
1714 state_array->ucNumEntries); in trinity_parse_power_table()
1717 power_state_offset = (u8 *)state_array->states; in trinity_parse_power_table()
1718 for (i = 0; i < state_array->ucNumEntries; i++) { in trinity_parse_power_table()
1755 rdev->pm.dpm.num_ps = state_array->ucNumEntries; in trinity_parse_power_table()
H A Dsumo_dpm.c1457 struct _StateArray *state_array; in sumo_parse_power_table() local
1472 state_array = (struct _StateArray *) in sumo_parse_power_table()
1483 state_array->ucNumEntries); in sumo_parse_power_table()
1486 power_state_offset = (u8 *)state_array->states; in sumo_parse_power_table()
1487 for (i = 0; i < state_array->ucNumEntries; i++) { in sumo_parse_power_table()
1523 rdev->pm.dpm.num_ps = state_array->ucNumEntries; in sumo_parse_power_table()
H A Dkv_dpm.c2435 struct _StateArray *state_array; in kv_parse_power_table() local
2450 state_array = (struct _StateArray *) in kv_parse_power_table()
2461 state_array->ucNumEntries); in kv_parse_power_table()
2464 power_state_offset = (u8 *)state_array->states; in kv_parse_power_table()
2465 for (i = 0; i < state_array->ucNumEntries; i++) { in kv_parse_power_table()
2500 rdev->pm.dpm.num_ps = state_array->ucNumEntries; in kv_parse_power_table()
H A Dradeon_atombios.c2665 struct _StateArray *state_array; in radeon_atombios_parse_power_table_6() local
2681 state_array = (struct _StateArray *) in radeon_atombios_parse_power_table_6()
2690 if (state_array->ucNumEntries == 0) in radeon_atombios_parse_power_table_6()
2693 state_array->ucNumEntries); in radeon_atombios_parse_power_table_6()
2696 power_state_offset = (u8 *)state_array->states; in radeon_atombios_parse_power_table_6()
2697 for (i = 0; i < state_array->ucNumEntries; i++) { in radeon_atombios_parse_power_table_6()
H A Dsi_dpm.c6758 struct _StateArray *state_array; in si_parse_power_table() local
6773 state_array = (struct _StateArray *) in si_parse_power_table()
6784 state_array->ucNumEntries); in si_parse_power_table()
6787 power_state_offset = (u8 *)state_array->states; in si_parse_power_table()
6788 for (i = 0; i < state_array->ucNumEntries; i++) { in si_parse_power_table()
6823 rdev->pm.dpm.num_ps = state_array->ucNumEntries; in si_parse_power_table()
H A Dci_dpm.c5497 struct _StateArray *state_array; in ci_parse_power_table() local
5513 state_array = (struct _StateArray *) in ci_parse_power_table()
5524 state_array->ucNumEntries); in ci_parse_power_table()
5527 power_state_offset = (u8 *)state_array->states; in ci_parse_power_table()
5529 for (i = 0; i < state_array->ucNumEntries; i++) { in ci_parse_power_table()
/linux/drivers/gpu/drm/amd/pm/legacy-dpm/
H A Dkv_dpm.c2700 struct _StateArray *state_array; in kv_parse_power_table() local
2717 state_array = (struct _StateArray *) in kv_parse_power_table()
2728 state_array->ucNumEntries); in kv_parse_power_table()
2731 power_state_offset = (u8 *)state_array->states; in kv_parse_power_table()
2732 for (i = 0; i < state_array->ucNumEntries; i++) { in kv_parse_power_table()
2763 adev->pm.dpm.num_ps = state_array->ucNumEntries; in kv_parse_power_table()
H A Dsi_dpm.c7319 struct _StateArray *state_array; in si_parse_power_table() local
7336 state_array = (struct _StateArray *) in si_parse_power_table()
7347 state_array->ucNumEntries); in si_parse_power_table()
7350 power_state_offset = (u8 *)state_array->states; in si_parse_power_table()
7351 for (adev->pm.dpm.num_ps = 0, i = 0; i < state_array->ucNumEntries; i++) { in si_parse_power_table()