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Searched refs:slcr (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/reset/
H A Dreset-zynq.c21 struct regmap *slcr; member
40 return regmap_update_bits(priv->slcr, in zynq_reset_assert()
57 return regmap_update_bits(priv->slcr, in zynq_reset_deassert()
76 ret = regmap_read(priv->slcr, priv->offset + (bank * 4), &reg); in zynq_reset_status()
98 priv->slcr = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, in zynq_reset_probe()
100 if (IS_ERR(priv->slcr)) { in zynq_reset_probe()
102 return PTR_ERR(priv->slcr); in zynq_reset_probe()
/linux/drivers/pci/controller/dwc/
H A Dpcie-amd-mdb.c65 void __iomem *slcr; member
91 writel_relaxed(val, pcie->slcr + AMD_MDB_TLP_IR_DISABLE_MISC); in amd_mdb_intx_irq_mask()
111 writel_relaxed(val, pcie->slcr + AMD_MDB_TLP_IR_ENABLE_MISC); in amd_mdb_intx_irq_unmask()
151 val = readl_relaxed(pcie->slcr + AMD_MDB_TLP_IR_STATUS_MISC); in dw_pcie_rp_intx()
186 writel_relaxed(val, pcie->slcr + AMD_MDB_TLP_IR_DISABLE_MISC); in amd_mdb_event_irq_mask()
200 writel_relaxed(val, pcie->slcr + AMD_MDB_TLP_IR_ENABLE_MISC); in amd_mdb_event_irq_unmask()
231 val = readl_relaxed(pcie->slcr + AMD_MDB_TLP_IR_STATUS_MISC); in amd_mdb_pcie_event()
232 val &= ~readl_relaxed(pcie->slcr + AMD_MDB_TLP_IR_MASK_MISC); in amd_mdb_pcie_event()
235 writel_relaxed(val, pcie->slcr + AMD_MDB_TLP_IR_STATUS_MISC); in amd_mdb_pcie_event()
259 pcie->slcr + AMD_MDB_TLP_IR_DISABLE_MISC); in amd_mdb_pcie_init_port()
[all …]
/linux/drivers/fpga/
H A Dzynq-fpga.c127 struct regmap *slcr; member
286 regmap_write(priv->slcr, SLCR_FPGA_RST_CTRL_OFFSET, in zynq_fpga_ops_write_init()
290 regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET, in zynq_fpga_ops_write_init()
293 regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET, in zynq_fpga_ops_write_init()
513 regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET, in zynq_fpga_ops_write_complete()
517 regmap_write(priv->slcr, SLCR_FPGA_RST_CTRL_OFFSET, in zynq_fpga_ops_write_complete()
569 priv->slcr = syscon_regmap_lookup_by_phandle(dev->of_node, in zynq_fpga_probe()
571 if (IS_ERR(priv->slcr)) { in zynq_fpga_probe()
573 return PTR_ERR(priv->slcr); in zynq_fpga_probe()
/linux/Documentation/devicetree/bindings/reset/
H A Dzynq-reset.txt10 - syscon: <&slcr>
21 syscon = <&slcr>;
/linux/drivers/clk/zynq/
H A Dclkc.c580 struct device_node *slcr; in zynq_clock_init() local
594 slcr = of_get_parent(np); in zynq_clock_init()
596 if (slcr->data) { in zynq_clock_init()
597 zynq_clkc_base = (__force void __iomem *)slcr->data + res.start; in zynq_clock_init()
600 of_node_put(slcr); in zynq_clock_init()
606 of_node_put(slcr); in zynq_clock_init()
/linux/arch/arm/boot/dts/xilinx/
H A Dzynq-7000.dtsi334 slcr: slcr@f8000000 { label
338 compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
364 syscon = <&slcr>;
370 syscon = <&slcr>;
399 syscon = <&slcr>;
/linux/arch/arm/mach-zynq/
H A DMakefile7 obj-y := common.o slcr.o pm.o
/linux/drivers/net/ethernet/mellanox/mlxsw/
H A Dspectrum.c2612 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl); in mlxsw_sp_lag_init()