| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | gfx_v9_0.h | 29 void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num,
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| H A D | soc24.c | 138 u32 sh_num, u32 reg_offset) in soc24_get_register_value() argument
141 return amdgpu_read_indexed_register(adev, se_num, sh_num, reg_offset); in soc24_get_register_value()
151 u32 sh_num, u32 reg_offset, u32 *value) in soc24_read_register() argument
167 se_num, sh_num, reg_offset); in soc24_read_register()
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| H A D | soc21.c | 312 u32 sh_num, u32 reg_offset) in soc21_get_register_value() argument
315 return amdgpu_read_indexed_register(adev, se_num, sh_num, reg_offset); in soc21_get_register_value()
324 u32 sh_num, u32 reg_offset, u32 *value) in soc21_read_register() argument
340 se_num, sh_num, reg_offset); in soc21_read_register()
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| H A D | gfx_v12_1.c | 203 u32 sh_num, u32 instance, int xcc_id);
1609 u32 sh_num, u32 instance, int xcc_id) in gfx_v12_1_xcc_select_se_sh() argument
1626 if (sh_num == 0xffffffff) in gfx_v12_1_xcc_select_se_sh()
1630 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); in gfx_v12_1_xcc_select_se_sh()
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| H A D | gfx_v12_0.c | 278 u32 sh_num, u32 instance, int xcc_id);
1686 u32 sh_num, u32 instance, int xcc_id) in gfx_v12_0_select_se_sh() argument
1703 if (sh_num == 0xffffffff) in gfx_v12_0_select_se_sh()
1707 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); in gfx_v12_0_select_se_sh()
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| H A D | gfx_v9_4_3.c | 689 u32 sh_num, u32 instance, int xcc_id) in gfx_v9_4_3_xcc_select_se_sh() argument
706 if (sh_num == 0xffffffff) in gfx_v9_4_3_xcc_select_se_sh()
710 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v9_4_3_xcc_select_se_sh()
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| H A D | gfx_v11_0.c | 352 u32 sh_num, u32 instance, int xcc_id);
2011 u32 sh_num, u32 instance, int xcc_id) in gfx_v11_0_select_se_sh() argument
2028 if (sh_num == 0xffffffff) in gfx_v11_0_select_se_sh()
2032 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); in gfx_v11_0_select_se_sh()
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| H A D | gfx_v8_0.c | 3401 u32 se_num, u32 sh_num, u32 instance, in gfx_v8_0_select_se_sh() argument
3416 if (sh_num == 0xffffffff) in gfx_v8_0_select_se_sh()
3419 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v8_0_select_se_sh()
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| H A D | gfx_v9_0.c | 2503 void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, in gfx_v9_0_select_se_sh() argument
2518 if (sh_num == 0xffffffff) in gfx_v9_0_select_se_sh()
2521 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v9_0_select_se_sh()
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| H A D | gfx_v10_0.c | 3686 u32 sh_num, u32 instance, int xcc_id);
5059 u32 sh_num, u32 instance, int xcc_id) in gfx_v10_0_select_se_sh() argument
5076 if (sh_num == 0xffffffff) in gfx_v10_0_select_se_sh()
5080 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); in gfx_v10_0_select_se_sh()
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