| /linux/drivers/gpu/drm/amd/amdkfd/ |
| H A D | kfd_pm4_headers.h | 75 uint32_t sh_mem_bases; member
125 uint32_t sh_mem_bases; member
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| H A D | kfd_pm4_headers_aldebaran.h | 54 uint32_t sh_mem_bases; member
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| H A D | kfd_pm4_headers_vi.h | 172 uint32_t sh_mem_bases; member
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| H A D | kfd_priv.h | 694 uint32_t sh_mem_bases; member
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| H A D | kfd_device_queue_manager.c | 156 qpd->sh_mem_bases, xcc_id); in program_sh_mem_settings()
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_amdkfd_gfx_v7.c | 81 uint32_t sh_mem_bases, uint32_t inst) in kgd_program_sh_mem_settings() argument
88 WREG32(mmSH_MEM_BASES, sh_mem_bases); in kgd_program_sh_mem_settings()
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| H A D | amdgpu_amdkfd_gfx_v8.c | 75 uint32_t sh_mem_bases, uint32_t inst) in kgd_program_sh_mem_settings() argument
82 WREG32(mmSH_MEM_BASES, sh_mem_bases); in kgd_program_sh_mem_settings()
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| H A D | amdgpu_amdkfd_gfx_v10_3.c | 84 uint32_t sh_mem_bases, uint32_t inst) in program_sh_mem_settings_v10_3() argument
89 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); in program_sh_mem_settings_v10_3()
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| H A D | amdgpu_amdkfd_gfx_v11.c | 82 uint32_t sh_mem_bases, uint32_t inst) in program_sh_mem_settings_v11() argument
87 WREG32(SOC15_REG_OFFSET(GC, 0, regSH_MEM_BASES), sh_mem_bases); in program_sh_mem_settings_v11()
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| H A D | amdgpu_amdkfd_gfx_v10.c | 84 uint32_t sh_mem_bases, uint32_t inst) in kgd_program_sh_mem_settings() argument
89 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); in kgd_program_sh_mem_settings()
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| H A D | amdgpu_amdkfd_gfx_v9.c | 90 uint32_t sh_mem_bases, uint32_t inst) in kgd_gfx_v9_program_sh_mem_settings() argument
95 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmSH_MEM_BASES, sh_mem_bases); in kgd_gfx_v9_program_sh_mem_settings()
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| H A D | gfx_v12_1.c | 1410 uint32_t sh_mem_bases; in gfx_v12_1_xcc_init_compute_vmid() local
1418 sh_mem_bases = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, in gfx_v12_1_xcc_init_compute_vmid()
1420 sh_mem_bases = REG_SET_FIELD(sh_mem_bases, SH_MEM_BASES, SHARED_BASE, in gfx_v12_1_xcc_init_compute_vmid()
1428 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases); in gfx_v12_1_xcc_init_compute_vmid()
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| H A D | gfx_v12_0.c | 1776 uint32_t sh_mem_bases; in gfx_v12_0_init_compute_vmid() local
1785 sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) | in gfx_v12_0_init_compute_vmid()
1793 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); in gfx_v12_0_init_compute_vmid()
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| H A D | gfx_v11_0.c | 2081 uint32_t sh_mem_bases; in gfx_v11_0_init_compute_vmid() local
2090 sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) | in gfx_v11_0_init_compute_vmid()
2098 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); in gfx_v11_0_init_compute_vmid()
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| H A D | gfx_v9_0.c | 2593 uint32_t sh_mem_bases; in gfx_v9_0_init_compute_vmid() local
2601 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); in gfx_v9_0_init_compute_vmid()
2612 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, sh_mem_bases); in gfx_v9_0_init_compute_vmid()
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