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Searched refs:set_drr (Results 1 – 25 of 30) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
H A Ddcn10_init.c61 .set_drr = dcn10_set_drr,
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
H A Ddcn201_init.c63 .set_drr = dcn10_set_drr,
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn21/
H A Ddcn21_init.c64 .set_drr = dcn10_set_drr,
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
H A Ddcn20_init.c64 .set_drr = dcn10_set_drr,
H A Ddcn20_hwseq.c955 if (pipe_ctx->stream_res.tg->funcs->set_drr) in dcn20_enable_stream_timing()
956 pipe_ctx->stream_res.tg->funcs->set_drr( in dcn20_enable_stream_timing()
2852 if (pipe_ctx->stream_res.tg->funcs->set_drr) in dcn20_reset_back_end_for_pipe()
2853 pipe_ctx->stream_res.tg->funcs->set_drr( in dcn20_reset_back_end_for_pipe()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn301/
H A Ddcn301_init.c66 .set_drr = dcn10_set_drr,
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn31/
H A Ddcn31_init.c68 .set_drr = dcn10_set_drr,
H A Ddcn31_hwseq.c541 if (pipe_ctx->stream_res.tg->funcs->set_drr) in dcn31_reset_back_end_for_pipe()
542 pipe_ctx->stream_res.tg->funcs->set_drr( in dcn31_reset_back_end_for_pipe()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn314/
H A Ddcn314_init.c70 .set_drr = dcn10_set_drr,
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
H A Ddcn30_init.c65 .set_drr = dcn10_set_drr,
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
H A Ddcn35_init.c72 .set_drr = dcn35_set_drr,
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn351/
H A Ddcn351_init.c71 .set_drr = dcn35_set_drr,
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_init.c46 .set_drr = dcn10_set_drr,
H A Ddcn401_hwseq.c834 if (pipe_ctx->stream_res.tg->funcs->set_drr) in dcn401_enable_stream_timing()
835 pipe_ctx->stream_res.tg->funcs->set_drr( in dcn401_enable_stream_timing()
1866 if (pipe_ctx->stream_res.tg->funcs->set_drr) in dcn401_reset_back_end_for_pipe()
1867 pipe_ctx->stream_res.tg->funcs->set_drr( in dcn401_reset_back_end_for_pipe()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
H A Ddcn32_init.c67 .set_drr = dcn10_set_drr,
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn201/
H A Ddcn201_optc.c162 .set_drr = optc1_set_drr,
/linux/drivers/gpu/drm/amd/display/dc/dce80/
H A Ddce80_timing_generator.c212 .set_drr = dce110_timing_generator_set_drr,
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn314/
H A Ddcn314_optc.c227 .set_drr = optc31_set_drr,
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn31/
H A Ddcn31_optc.c279 .set_drr = optc31_set_drr,
/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dtiming_generator.h246 void (*set_drr)(struct timing_generator *tg, const struct drr_params *params); member
/linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/
H A Ddce110_hwseq.c1657 if (pipe_ctx->stream_res.tg->funcs->set_drr) in dce110_apply_single_controller_ctx_to_hw()
1658 pipe_ctx->stream_res.tg->funcs->set_drr( in dce110_apply_single_controller_ctx_to_hw()
2082 static void set_drr(struct pipe_ctx **pipe_ctx, in set_drr() function
2107 if (tg->funcs->set_drr) in set_drr()
2108 tg->funcs->set_drr(tg, &params); in set_drr()
3350 .set_drr = set_drr,
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn20/
H A Ddcn20_optc.c537 .set_drr = optc1_set_drr,
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn35/
H A Ddcn35_optc.c463 .set_drr = optc35_set_drr,
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn401/
H A Ddcn401_optc.c494 .set_drr = optc401_set_drr,
/linux/drivers/gpu/drm/amd/display/dc/hwss/
H A Dhw_sequencer.h273 void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes, member

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