| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | soc21.c | 310 bool indexed, u32 se_num, in soc21_read_indexed_register()
314 return amdgpu_read_indexed_register(adev, se_num, sh_num, reg_offset); in soc21_read_indexed_register()
322 static int soc21_read_register(struct amdgpu_device *adev, u32 se_num, in soc21_read_indexed_register()
339 se_num, sh_num, reg_offset); in soc21_read_register() argument
309 soc21_read_indexed_register(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 reg_offset) soc21_read_indexed_register() argument
327 soc21_get_register_value(struct amdgpu_device * adev,bool indexed,u32 se_num,u32 sh_num,u32 reg_offset) soc21_get_register_value() argument
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| H A D | gfx_v9_0.h | 29 void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num,
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| H A D | amdgpu_kms.c | 876 unsigned int se_num = (info->read_mmr_reg.instance >> in amdgpu_info_ioctl() local
889 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) in amdgpu_info_ioctl()
890 se_num = 0xffffffff; in amdgpu_info_ioctl()
891 else if (se_num >= AMDGPU_GFX_MAX_SE) in amdgpu_info_ioctl()
912 if (amdgpu_asic_read_register(adev, se_num, sh_num, in amdgpu_info_ioctl()
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| H A D | gfx_v6_0.c | 1304 static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, in gfx_v6_0_select_se_sh() argument
1314 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) in gfx_v6_0_select_se_sh()
1317 else if (se_num == 0xffffffff) in gfx_v6_0_select_se_sh()
1322 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); in gfx_v6_0_select_se_sh()
1325 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); in gfx_v6_0_select_se_sh()
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| H A D | gfx_v12_1.c | 81 static void gfx_v12_1_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1330 static void gfx_v12_1_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num, in gfx_v12_1_xcc_select_se_sh()
1342 if (se_num == 0xffffffff) in gfx_v12_1_get_sa_active_bitmap()
1346 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v12_1_get_sa_active_bitmap()
1305 gfx_v12_1_xcc_select_se_sh(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 instance,int xcc_id) gfx_v12_1_xcc_select_se_sh() argument
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| H A D | amdgpu.h | 570 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
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| H A D | gfx_v12_0.c | 277 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1674 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, in gfx_v12_0_select_se_sh() argument
1686 if (se_num == 0xffffffff) in gfx_v12_0_select_se_sh()
1690 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v12_0_select_se_sh()
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| H A D | gfx_v9_0.c | 2502 void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, in gfx_v9_0_select_se_sh() argument
2512 if (se_num == 0xffffffff) in gfx_v9_0_select_se_sh()
2515 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v9_0_select_se_sh()
7023 for (j = 0; j < gfx_v9_0_edc_counter_regs[i].se_num; j++) { in gfx_v9_0_reset_ras_error_count()
7085 for (j = 0; j < gfx_v9_0_edc_counter_regs[i].se_num; j++) { in gfx_v9_0_query_ras_error_count()
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| H A D | gfx_v11_0.c | 343 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1984 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, in gfx_v11_0_select_se_sh()
1996 if (se_num == 0xffffffff) in gfx_v11_0_select_se_sh()
2000 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v11_0_select_se_sh()
1978 gfx_v11_0_select_se_sh(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 instance,int xcc_id) gfx_v11_0_select_se_sh() argument
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