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Searched refs:se_num (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_0.h29 void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num,
H A Dsoc15.c404 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num, in soc15_read_indexed_register() argument
410 if (se_num != 0xffffffff || sh_num != 0xffffffff) in soc15_read_indexed_register()
411 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); in soc15_read_indexed_register()
415 if (se_num != 0xffffffff || sh_num != 0xffffffff) in soc15_read_indexed_register()
422 bool indexed, u32 se_num, in soc15_get_register_value() argument
426 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); in soc15_get_register_value()
436 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num, in soc15_read_register() argument
453 se_num, sh_num, reg_offset); in soc15_read_register()
H A Damdgpu_kms.c843 unsigned int se_num = (info->read_mmr_reg.instance >> in amdgpu_info_ioctl() local
856 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) { in amdgpu_info_ioctl()
857 se_num = 0xffffffff; in amdgpu_info_ioctl()
858 } else if (se_num >= AMDGPU_GFX_MAX_SE) { in amdgpu_info_ioctl()
885 if (amdgpu_asic_read_register(adev, se_num, sh_num, in amdgpu_info_ioctl()
H A Dgfx_v6_0.c1304 static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, in gfx_v6_0_select_se_sh() argument
1314 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) in gfx_v6_0_select_se_sh()
1317 else if (se_num == 0xffffffff) in gfx_v6_0_select_se_sh()
1322 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); in gfx_v6_0_select_se_sh()
1325 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); in gfx_v6_0_select_se_sh()
H A Dgfx_v7_0.c1559 u32 se_num, u32 sh_num, u32 instance, in gfx_v7_0_select_se_sh() argument
1569 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) in gfx_v7_0_select_se_sh()
1572 else if (se_num == 0xffffffff) in gfx_v7_0_select_se_sh()
1577 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); in gfx_v7_0_select_se_sh()
1580 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); in gfx_v7_0_select_se_sh()
H A Dgfx_v12_0.c277 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1661 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, in gfx_v12_0_select_se_sh() argument
1673 if (se_num == 0xffffffff) in gfx_v12_0_select_se_sh()
1677 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v12_0_select_se_sh()
H A Damdgpu.h664 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
H A Dgfx_v11_0.c330 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1947 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, in gfx_v11_0_select_se_sh() argument
1959 if (se_num == 0xffffffff) in gfx_v11_0_select_se_sh()
1963 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v11_0_select_se_sh()