Searched refs:sclk_setting (Results 1 – 1 of 1) sorted by relevance
720 uint32_t clock, SMU_SclkSetting *sclk_setting) in vegam_calculate_sclk_params() argument731 sclk_setting->SclkFrequency = clock; in vegam_calculate_sclk_params()735 sclk_setting->Fcw_int = dividers.usSclk_fcw_int; in vegam_calculate_sclk_params()736 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac; in vegam_calculate_sclk_params()737 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int; in vegam_calculate_sclk_params()738 sclk_setting->PllRange = dividers.ucSclkPllRange; in vegam_calculate_sclk_params()739 sclk_setting->Sclk_slew_rate = 0x400; in vegam_calculate_sclk_params()740 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac; in vegam_calculate_sclk_params()741 sclk_setting->Pcc_down_slew_rate = 0xffff; in vegam_calculate_sclk_params()742 sclk_setting->SSc_En = dividers.ucSscEnable; in vegam_calculate_sclk_params()[all …]