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Searched refs:rvu (Results 1 – 24 of 24) sorted by relevance

/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Drvu_cgx.c26 *otx2_mbox_alloc_msg_ ## _fn_name(struct rvu *rvu, int devid) \
31 &rvu->afpf_wq_info.mbox_up, devid, sizeof(struct _req_type), \
37 trace_otx2_msg_alloc(rvu->pdev, _id, sizeof(*req), 0); \
44 bool is_mac_feature_supported(struct rvu *rvu, int pf, int feature) in is_mac_feature_supported() argument
49 if (!is_pf_cgxmapped(rvu, pf)) in is_mac_feature_supported()
52 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); in is_mac_feature_supported()
53 cgxd = rvu_cgx_pdata(cgx_id, rvu); in is_mac_feature_supported()
58 #define CGX_OFFSET(x) ((x) * rvu->hw->lmac_per_cgx)
60 static u64 cgxlmac_to_pfmap(struct rvu *rvu, u8 cgx_id, u8 lmac_id) in cgxlmac_to_pfmap() argument
62 return rvu->cgxlmac2pf_map[CGX_OFFSET(cgx_id) + lmac_id]; in cgxlmac_to_pfmap()
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H A Drvu.c29 static void rvu_set_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf,
31 static void rvu_clear_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf,
33 static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc);
35 static int rvu_mbox_init(struct rvu *rvu, struct mbox_wq_info *mw,
61 static void rvu_setup_hw_capabilities(struct rvu *rvu) in rvu_setup_hw_capabilities() argument
63 struct rvu_hwinfo *hw = rvu->hw; in rvu_setup_hw_capabilities()
73 hw->rvu = rvu; in rvu_setup_hw_capabilities()
75 if (is_rvu_pre_96xx_C0(rvu)) { in rvu_setup_hw_capabilities()
82 if (is_rvu_96xx_A0(rvu) || is_rvu_95xx_A0(rvu)) in rvu_setup_hw_capabilities()
85 if (!is_rvu_pre_96xx_C0(rvu)) in rvu_setup_hw_capabilities()
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H A Drvu_cpt.c35 reg = rvu_read64(rvu, blkaddr, CPT_AF_EXEX_STS(e)); \
50 static u16 cpt_max_engines_get(struct rvu *rvu) in cpt_max_engines_get() argument
55 reg = rvu_read64(rvu, BLKADDR_CPT0, CPT_AF_CONSTANTS1); in cpt_max_engines_get()
66 static int cpt_10k_flt_nvecs_get(struct rvu *rvu, u16 max_engs) in cpt_10k_flt_nvecs_get() argument
73 dev_warn_once(rvu->dev, "flt_vecs:%d exceeds the max vectors:%d\n", in cpt_10k_flt_nvecs_get()
84 struct rvu *rvu = block->rvu; in cpt_af_flt_intr_handler() local
90 reg = rvu_read64(rvu, blkaddr, CPT_AF_FLTX_INT(vec)); in cpt_af_flt_intr_handler()
91 dev_err_ratelimited(rvu->dev, "Received CPTAF FLT%d irq : 0x%llx", vec, reg); in cpt_af_flt_intr_handler()
106 grp = rvu_read64(rvu, blkaddr, CPT_AF_EXEX_CTL2(eng)) & 0xFF; in cpt_af_flt_intr_handler()
108 rvu_write64(rvu, blkaddr, CPT_AF_EXEX_CTL2(eng), 0x0); in cpt_af_flt_intr_handler()
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H A Drvu_devlink.c29 static bool rvu_common_request_irq(struct rvu *rvu, int offset, in rvu_common_request_irq() argument
32 struct rvu_devlink *rvu_dl = rvu->rvu_dl; in rvu_common_request_irq()
35 sprintf(&rvu->irq_name[offset * NAME_SIZE], "%s", name); in rvu_common_request_irq()
36 rc = request_irq(pci_irq_vector(rvu->pdev, offset), fn, 0, in rvu_common_request_irq()
37 &rvu->irq_name[offset * NAME_SIZE], rvu_dl); in rvu_common_request_irq()
39 dev_warn(rvu->dev, "Failed to register %s irq\n", name); in rvu_common_request_irq()
41 rvu->irq_allocated[offset] = true; in rvu_common_request_irq()
43 return rvu->irq_allocated[offset]; in rvu_common_request_irq()
60 struct rvu *rvu; in rvu_nix_af_rvu_intr_handler() local
64 rvu = rvu_dl->rvu; in rvu_nix_af_rvu_intr_handler()
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H A Drvu_rep.c19 *otx2_mbox_alloc_msg_ ## _fn_name(struct rvu *rvu, int devid) \
24 &rvu->afpf_wq_info.mbox_up, devid, sizeof(struct _req_type), \
36 static int rvu_rep_up_notify(struct rvu *rvu, struct rep_event *event) in rvu_rep_up_notify() argument
38 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, event->pcifunc); in rvu_rep_up_notify()
42 pf = rvu_get_pf(rvu->pdev, event->pcifunc); in rvu_rep_up_notify()
47 mutex_lock(&rvu->mbox_lock); in rvu_rep_up_notify()
48 msg = otx2_mbox_alloc_msg_rep_event_up_notify(rvu, pf); in rvu_rep_up_notify()
50 mutex_unlock(&rvu->mbox_lock); in rvu_rep_up_notify()
59 otx2_mbox_wait_for_zero(&rvu->afpf_wq_info.mbox_up, pf); in rvu_rep_up_notify()
61 otx2_mbox_msg_send_up(&rvu->afpf_wq_info.mbox_up, pf); in rvu_rep_up_notify()
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H A Drvu_npc_hash.c103 static u64 npc_update_use_hash(struct rvu *rvu, int blkaddr, in npc_update_use_hash() argument
109 cfg = rvu_read64(rvu, blkaddr, NPC_AF_INTFX_LIDX_LTX_LDX_CFG(intf, lid, lt, ld)); in npc_update_use_hash()
122 static void npc_program_mkex_hash_rx(struct rvu *rvu, int blkaddr, in npc_program_mkex_hash_rx() argument
125 struct npc_mcam_kex_hash *mkex_hash = rvu->kpu.mkex_hash; in npc_program_mkex_hash_rx()
141 cfg = npc_update_use_hash(rvu, blkaddr, in npc_program_mkex_hash_rx()
162 static void npc_program_mkex_hash_tx(struct rvu *rvu, int blkaddr, in npc_program_mkex_hash_tx() argument
165 struct npc_mcam_kex_hash *mkex_hash = rvu->kpu.mkex_hash; in npc_program_mkex_hash_tx()
181 cfg = npc_update_use_hash(rvu, blkaddr, in npc_program_mkex_hash_tx()
200 void npc_config_secret_key(struct rvu *rvu, int blkaddr) in npc_config_secret_key() argument
202 struct hw_cap *hwcap = &rvu->hw->cap; in npc_config_secret_key()
[all …]
H A Drvu_nix.c20 static void nix_free_tx_vtag_entries(struct rvu *rvu, u16 pcifunc);
21 static int rvu_nix_get_bpid(struct rvu *rvu, struct nix_bp_cfg_req *req,
23 static int nix_update_mce_rule(struct rvu *rvu, u16 pcifunc,
25 static int nix_setup_ipolicers(struct rvu *rvu,
27 static void nix_ipolicer_freemem(struct rvu *rvu, struct nix_hw *nix_hw);
30 static int nix_free_all_bandprof(struct rvu *rvu, u16 pcifunc);
31 static void nix_clear_ratelimit_aggr(struct rvu *rvu, struct nix_hw *nix_hw,
34 static int nix_get_tx_link(struct rvu *rvu, u16 pcifunc);
91 int rvu_get_next_nix_blkaddr(struct rvu *rvu, int blkaddr) in rvu_get_next_nix_blkaddr() argument
97 return rvu->nix_blkaddr[blkaddr]; in rvu_get_next_nix_blkaddr()
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H A Drvu_cn10k.c23 static int lmtst_map_table_ops(struct rvu *rvu, u32 index, u64 *val, in lmtst_map_table_ops() argument
30 tbl_base = rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_MAP_BASE); in lmtst_map_table_ops()
31 cfg = rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_CFG); in lmtst_map_table_ops()
37 dev_err(rvu->dev, "Failed to setup lmt map table mapping!!\n"); in lmtst_map_table_ops()
57 rvu_write64(rvu, BLKADDR_APR, APR_AF_LMT_CTL, BIT_ULL(0)); in lmtst_map_table_ops()
58 rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_CTL); in lmtst_map_table_ops()
59 rvu_write64(rvu, BLKADDR_APR, APR_AF_LMT_CTL, 0x00); in lmtst_map_table_ops()
67 static u32 rvu_get_lmtst_tbl_index(struct rvu *rvu, u16 pcifunc) in rvu_get_lmtst_tbl_index() argument
69 return ((rvu_get_pf(rvu->pdev, pcifunc) * LMT_MAX_VFS) + in rvu_get_lmtst_tbl_index()
73 static int rvu_get_lmtaddr(struct rvu *rvu, u16 pcifunc, in rvu_get_lmtaddr() argument
[all …]
H A Dmcs_rvu_if.c19 *otx2_mbox_alloc_msg_ ## _fn_name(struct rvu *rvu, int devid) \
24 &rvu->afpf_wq_info.mbox_up, devid, sizeof(struct _req_type), \
36 void rvu_mcs_ptp_cfg(struct rvu *rvu, u8 rpm_id, u8 lmac_id, bool ena) in rvu_mcs_ptp_cfg() argument
42 if (!rvu->mcs_blk_cnt) in rvu_mcs_ptp_cfg()
51 if (rvu->mcs_blk_cnt > 1) { in rvu_mcs_ptp_cfg()
63 port = (rpm_id * rvu->hw->lmac_per_cgx) + lmac_id; in rvu_mcs_ptp_cfg()
72 int rvu_mbox_handler_mcs_set_lmac_mode(struct rvu *rvu, in rvu_mbox_handler_mcs_set_lmac_mode() argument
78 if (req->mcs_id >= rvu->mcs_blk_cnt) in rvu_mbox_handler_mcs_set_lmac_mode()
93 struct rvu *rvu = mcs->rvu; in mcs_add_intr_wq_entry() local
98 pfvf = &mcs->vf[rvu_get_hwvf(rvu, pcifunc)]; in mcs_add_intr_wq_entry()
[all …]
H A Drvu_switch.c11 void rvu_switch_enable_lbk_link(struct rvu *rvu, u16 pcifunc, bool enable) in rvu_switch_enable_lbk_link() argument
13 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); in rvu_switch_enable_lbk_link()
16 nix_hw = get_nix_hw(rvu->hw, pfvf->nix_blkaddr); in rvu_switch_enable_lbk_link()
18 rvu_nix_tx_tl2_cfg(rvu, pfvf->nix_blkaddr, pcifunc, in rvu_switch_enable_lbk_link()
22 static int rvu_switch_install_rx_rule(struct rvu *rvu, u16 pcifunc, in rvu_switch_install_rx_rule() argument
29 pfvf = rvu_get_pfvf(rvu, pcifunc); in rvu_switch_install_rx_rule()
48 return rvu_mbox_handler_npc_install_flow(rvu, &req, &rsp); in rvu_switch_install_rx_rule()
51 static int rvu_switch_install_tx_rule(struct rvu *rvu, u16 pcifunc, u16 entry) in rvu_switch_install_tx_rule() argument
58 pfvf = rvu_get_pfvf(rvu, pcifunc); in rvu_switch_install_tx_rule()
66 rvu_switch_enable_lbk_link(rvu, pcifunc, true); in rvu_switch_install_tx_rule()
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H A Drvu_npc.c32 static void npc_mcam_free_all_entries(struct rvu *rvu, struct npc_mcam *mcam,
34 static void npc_mcam_free_all_counters(struct rvu *rvu, struct npc_mcam *mcam,
47 bool is_npc_interface_valid(struct rvu *rvu, u8 intf) in is_npc_interface_valid() argument
49 struct rvu_hwinfo *hw = rvu->hw; in is_npc_interface_valid()
54 int rvu_npc_get_tx_nibble_cfg(struct rvu *rvu, u64 nibble_ena) in rvu_npc_get_tx_nibble_cfg() argument
59 if (is_rvu_96xx_B0(rvu)) in rvu_npc_get_tx_nibble_cfg()
64 void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf) in rvu_npc_set_pkind() argument
69 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); in rvu_npc_set_pkind()
75 rvu_write64(rvu, blkaddr, NPC_AF_PKINDX_CPI_DEFX(pkind, 0), val); in rvu_npc_set_pkind()
78 int rvu_npc_get_pkind(struct rvu *rvu, u16 pf) in rvu_npc_get_pkind() argument
[all …]
H A Drvu_npc_hash.h27 rvu_write64(rvu, blkaddr, \
31 rvu_write64(rvu, blkaddr, \
35 rvu_read64(rvu, blkaddr, NPC_AF_INTFX_HASHX_RESULT_CTRL(intf, ld))
38 rvu_read64(rvu, blkaddr, NPC_AF_INTFX_HASHX_MASKX(intf, ld, mask_idx))
41 rvu_write64(rvu, blkaddr, \
55 void npc_update_field_hash(struct rvu *rvu, u8 intf,
63 void npc_config_secret_key(struct rvu *rvu, int blkaddr);
64 void npc_program_mkex_hash(struct rvu *rvu, int blkaddr);
208 bool rvu_npc_exact_has_match_table(struct rvu *rvu);
209 u32 rvu_npc_exact_get_max_entries(struct rvu *rvu);
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H A Drvu_sdp.c20 bool is_sdp_pfvf(struct rvu *rvu, u16 pcifunc) in is_sdp_pfvf() argument
22 u16 pf = rvu_get_pf(rvu->pdev, pcifunc); in is_sdp_pfvf()
37 bool is_sdp_pf(struct rvu *rvu, u16 pcifunc) in is_sdp_pf() argument
39 return (is_sdp_pfvf(rvu, pcifunc) && in is_sdp_pf()
44 bool is_sdp_vf(struct rvu *rvu, u16 pcifunc) in is_sdp_vf() argument
47 return (rvu->vf_devid == RVU_SDP_VF_DEVID); in is_sdp_vf()
49 return (is_sdp_pfvf(rvu, pcifunc) && in is_sdp_vf()
53 int rvu_sdp_init(struct rvu *rvu) in rvu_sdp_init() argument
59 if (rvu->fwdata && rvu->fwdata->channel_data.valid) { in rvu_sdp_init()
61 pfvf = &rvu->pf[sdp_pf_num[0]]; in rvu_sdp_init()
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H A Drvu_npc_fs.c60 bool npc_is_feature_supported(struct rvu *rvu, u64 features, u8 intf) in npc_is_feature_supported() argument
62 struct npc_mcam *mcam = &rvu->hw->mcam; in npc_is_feature_supported()
139 static bool npc_is_field_present(struct rvu *rvu, enum key_fields type, u8 intf) in npc_is_field_present() argument
141 struct npc_mcam *mcam = &rvu->hw->mcam; in npc_is_field_present()
198 static bool npc_check_overlap(struct rvu *rvu, int blkaddr, in npc_check_overlap() argument
201 struct npc_mcam *mcam = &rvu->hw->mcam; in npc_check_overlap()
218 cfg = rvu_read64(rvu, blkaddr, in npc_check_overlap()
247 static bool npc_check_field(struct rvu *rvu, int blkaddr, enum key_fields type, in npc_check_field() argument
250 if (!npc_is_field_present(rvu, type, intf) || in npc_check_field()
251 npc_check_overlap(rvu, blkaddr, type, 0, intf)) in npc_check_field()
[all …]
H A Dptp.c99 static bool is_tstmp_atomic_update_supported(struct rvu *rvu) in is_tstmp_atomic_update_supported() argument
101 struct ptp *ptp = rvu->ptp; in is_tstmp_atomic_update_supported()
103 if (is_rvu_otx2(rvu)) in is_tstmp_atomic_update_supported()
367 void ptp_start(struct rvu *rvu, u64 sclk, u32 ext_clk_freq, u32 extts) in ptp_start() argument
369 struct ptp *ptp = rvu->ptp; in ptp_start()
388 if (is_tstmp_atomic_update_supported(rvu)) { in ptp_start()
619 int rvu_mbox_handler_ptp_op(struct rvu *rvu, struct ptp_req *req, in rvu_mbox_handler_ptp_op() argument
631 if (!rvu->ptp) in rvu_mbox_handler_ptp_op()
636 err = ptp_adjfine(rvu->ptp, req->scaled_ppm); in rvu_mbox_handler_ptp_op()
639 err = ptp_get_clock(rvu->ptp, &rsp->clk); in rvu_mbox_handler_ptp_op()
[all …]
H A Drvu_devlink.h72 struct rvu *rvu; member
79 int rvu_register_dl(struct rvu *rvu);
80 void rvu_unregister_dl(struct rvu *rvu);
H A Dptp.h26 struct rvu;
29 void ptp_start(struct rvu *rvu, u64 sclk, u32 ext_clk_freq, u32 extts);
H A Drvu_npc_fs.h17 void npc_update_entry(struct rvu *rvu, enum key_fields type,
H A Drvu_reg.h642 if (rvu->hw->npc_ext_set) \
650 if (rvu->hw->npc_ext_set) \
658 if (rvu->hw->npc_ext_set) \
666 if (rvu->hw->npc_ext_set) \
674 if (rvu->hw->npc_ext_set) \
682 if (rvu->hw->npc_ext_set) \
690 if (rvu->hw->npc_ext_set) \
698 if (rvu->hw->npc_ext_set) \
H A Dnpc.h14 rvu_write64(rvu, blkaddr, \
18 rvu_write64(rvu, blkaddr, \
H A Dmcs.h150 void *rvu; member
/linux/drivers/net/ethernet/marvell/octeontx2/af/cn20k/
H A Dmbox_init.c19 struct rvu *rvu = rvu_irq_data->rvu; in cn20k_afvf_mbox_intr_handler() local
26 intr = rvupf_read64(rvu, rvu_irq_data->intr_status); in cn20k_afvf_mbox_intr_handler()
27 rvupf_write64(rvu, rvu_irq_data->intr_status, intr); in cn20k_afvf_mbox_intr_handler()
30 trace_otx2_msg_interrupt(rvu->pdev, "VF(s) to AF", intr); in cn20k_afvf_mbox_intr_handler()
32 rvu_irq_data->afvf_queue_work_hdlr(&rvu->afvf_wq_info, rvu_irq_data->start, in cn20k_afvf_mbox_intr_handler()
38 int cn20k_register_afvf_mbox_intr(struct rvu *rvu, int pf_vec_start) in cn20k_register_afvf_mbox_intr() argument
45 irq_data = devm_kcalloc(rvu->dev, 4, in cn20k_register_afvf_mbox_intr()
82 irq_data[vec].rvu = rvu; in cn20k_register_afvf_mbox_intr()
84 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAF VFAF%d Mbox%d", in cn20k_register_afvf_mbox_intr()
86 err = request_irq(pci_irq_vector(rvu->pdev, offset), in cn20k_register_afvf_mbox_intr()
[all …]
H A Dapi.h20 int cn20k_rvu_mbox_init(struct rvu *rvu, int type, int num);
21 int cn20k_rvu_get_mbox_regions(struct rvu *rvu, void **mbox_addr,
23 void cn20k_free_mbox_memory(struct rvu *rvu);
24 int cn20k_register_afpf_mbox_intr(struct rvu *rvu);
25 int cn20k_register_afvf_mbox_intr(struct rvu *rvu, int pf_vec_start);
26 void cn20k_rvu_enable_mbox_intr(struct rvu *rvu);
27 void cn20k_rvu_unregister_interrupts(struct rvu *rvu);
30 void cn20k_rvu_enable_afvf_intr(struct rvu *rvu, int vfs);
31 void cn20k_rvu_disable_afvf_intr(struct rvu *rvu, int vfs);
/linux/Documentation/networking/device_drivers/ethernet/marvell/
H A Docteontx2.rst425 The rvu representor driver implements support for offloading tc rules using port representors.