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Searched refs:register_base (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/net/mdio/
H A Dmdio-cavium.c21 smi_clk.u64 = oct_mdio_readq(p->register_base + SMI_CLK); in cavium_mdiobus_set_mode()
24 oct_mdio_writeq(smi_clk.u64, p->register_base + SMI_CLK); in cavium_mdiobus_set_mode()
39 oct_mdio_writeq(smi_wr.u64, p->register_base + SMI_WR_DAT); in cavium_mdiobus_c45_addr()
45 oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD); in cavium_mdiobus_c45_addr()
52 smi_wr.u64 = oct_mdio_readq(p->register_base + SMI_WR_DAT); in cavium_mdiobus_c45_addr()
73 oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD); in cavium_mdiobus_read_c22()
80 smi_rd.u64 = oct_mdio_readq(p->register_base + SMI_RD_DAT); in cavium_mdiobus_read_c22()
107 oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD); in cavium_mdiobus_read_c45()
114 smi_rd.u64 = oct_mdio_readq(p->register_base + SMI_RD_DAT); in cavium_mdiobus_read_c45()
136 oct_mdio_writeq(smi_wr.u64, p->register_base + SMI_WR_DAT); in cavium_mdiobus_write_c22()
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H A Dmdio-cavium.h93 void __iomem *register_base; member
/linux/drivers/gpio/
H A Dgpio-thunderx.c55 u8 __iomem *register_base; member
77 u64 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line)); in thunderx_gpio_is_gpio_nowarn()
114 txgpio->register_base + bit_cfg_reg(line)); in thunderx_gpio_dir_in()
126 void __iomem *reg = txgpio->register_base + in thunderx_gpio_set()
153 writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line)); in thunderx_gpio_dir_out()
172 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line)); in thunderx_gpio_get_direction()
191 void __iomem *reg = txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET; in thunderx_gpio_set_config()
202 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line)); in thunderx_gpio_set_config()
241 writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line)); in thunderx_gpio_set_config()
265 u64 read_bits = readq(txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_RX_DAT); in thunderx_gpio_get()
[all …]
H A Dgpio-octeon.c39 u64 register_base; member
46 cvmx_write_csr(gpio->register_base + bit_cfg_reg(offset), 0); in octeon_gpio_dir_in()
55 u64 reg = gpio->register_base + (value ? TX_SET : TX_CLEAR); in octeon_gpio_set()
72 cvmx_write_csr(gpio->register_base + bit_cfg_reg(offset), cfgx.u64); in octeon_gpio_dir_out()
79 u64 read_bits = cvmx_read_csr(gpio->register_base + RX_DAT); in octeon_gpio_get()
100 gpio->register_base = (u64)reg_base; in octeon_gpio_probe()
/linux/drivers/spi/
H A Dspi-cavium.c24 mpi_sts.u64 = readq(p->register_base + OCTEON_SPI_STS(p)); in octeon_spi_wait_ready()
66 writeq(mpi_cfg.u64, p->register_base + OCTEON_SPI_CFG(p)); in octeon_spi_do_transfer()
78 writeq(d, p->register_base + OCTEON_SPI_DAT0(p) + (8 * i)); in octeon_spi_do_transfer()
85 writeq(mpi_tx.u64, p->register_base + OCTEON_SPI_TX(p)); in octeon_spi_do_transfer()
90 u64 v = readq(p->register_base + OCTEON_SPI_DAT0(p) + (8 * i)); in octeon_spi_do_transfer()
102 writeq(d, p->register_base + OCTEON_SPI_DAT0(p) + (8 * i)); in octeon_spi_do_transfer()
113 writeq(mpi_tx.u64, p->register_base + OCTEON_SPI_TX(p)); in octeon_spi_do_transfer()
118 u64 v = readq(p->register_base + OCTEON_SPI_DAT0(p) + (8 * i)); in octeon_spi_do_transfer()
H A Dspi-cavium-thunderx.c41 p->register_base = pcim_iomap(pdev, 0, pci_resource_len(pdev, 0)); in thunderx_spi_probe()
42 if (!p->register_base) { in thunderx_spi_probe()
95 writeq(0, p->register_base + OCTEON_SPI_CFG(p)); in thunderx_spi_remove()
H A Dspi-cavium.h18 void __iomem *register_base; member
/linux/arch/x86/math-emu/
H A Dreg_ld_str.c1129 FPU_copy_from_user(register_base + offset, s, other); in FPU_frstor()
1131 FPU_copy_from_user(register_base, s + other, offset); in FPU_frstor()
1210 if (__copy_to_user(d, register_base + offset, other)) in fsave()
1213 if (__copy_to_user(d + other, register_base, offset)) in fsave()
/linux/drivers/scsi/aic7xxx/
H A Daic79xx.reg3567 * Reading this register is equivalent to reading (register_base + SINDEX) and
3578 * Writing this register is equivalent to writing to (register_base + DINDEX)