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Searched refs:reg_write (Results 1 – 25 of 175) sorted by relevance

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/linux/arch/x86/pci/
H A Dce4100.c60 static void reg_write(struct sim_dev_reg *reg, u32 value) in reg_write() function
98 DEFINE_REG(2, 0, 0x10, (16*MB), reg_init, reg_read, reg_write)
99 DEFINE_REG(2, 0, 0x14, (256), reg_init, reg_read, reg_write)
100 DEFINE_REG(2, 1, 0x10, (64*KB), reg_init, reg_read, reg_write)
101 DEFINE_REG(3, 0, 0x10, (64*KB), reg_init, reg_read, reg_write)
102 DEFINE_REG(4, 0, 0x10, (128*KB), reg_init, reg_read, reg_write)
103 DEFINE_REG(4, 1, 0x10, (128*KB), reg_init, reg_read, reg_write)
104 DEFINE_REG(6, 0, 0x10, (512*KB), reg_init, reg_read, reg_write)
105 DEFINE_REG(6, 1, 0x10, (512*KB), reg_init, reg_read, reg_write)
106 DEFINE_REG(6, 2, 0x10, (64*KB), reg_init, reg_read, reg_write)
[all …]
/linux/drivers/firewire/
H A Dinit_ohci1394_dma.c40 static inline void reg_write(const struct ohci *ohci, int offset, u32 data) in reg_write() function
58 reg_write(ohci, OHCI1394_PhyControl, (addr << 8) | 0x00008000); in get_phy_reg()
75 reg_write(ohci, OHCI1394_PhyControl, (addr << 8) | data | 0x00004000); in set_phy_reg()
89 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset); in init_ohci1394_soft_reset()
114 reg_write(ohci, OHCI1394_BusOptions, bus_options); in init_ohci1394_initialize()
117 reg_write(ohci, OHCI1394_NodeID, 0x0000ffc0); in init_ohci1394_initialize()
120 reg_write(ohci, OHCI1394_HCControlSet, in init_ohci1394_initialize()
124 reg_write(ohci, OHCI1394_LinkControlClear, 0xffffffff); in init_ohci1394_initialize()
127 reg_write(ohci, OHCI1394_LinkControlSet, in init_ohci1394_initialize()
131 reg_write(ohci, OHCI1394_LinkControlClear, 0x00000400); in init_ohci1394_initialize()
[all …]
H A Dnosy.c216 reg_write(struct pcilynx *lynx, int offset, u32 data) in reg_write() function
230 reg_write(lynx, offset, (reg_read(lynx, offset) | mask)); in reg_set_bits()
241 reg_write(lynx, DMA0_CURRENT_PCL + dmachan * 0x20, pcl_bus); in run_pcl()
242 reg_write(lynx, DMA0_CHAN_CTRL + dmachan * 0x20, in run_pcl()
259 reg_write(lynx, LINK_PHY, LINK_PHY_WRITE | in set_phy_reg()
477 reg_write(lynx, LINK_INT_STATUS, link_int_status); in irq_handler()
487 reg_write(lynx, PCI_INT_STATUS, pci_int_status); in irq_handler()
508 reg_write(lynx, PCI_INT_ENABLE, 0); in remove_card()
605 reg_write(lynx, DMA0_CHAN_CTRL, 0); in add_card()
606 reg_write(lynx, DMA_GLOBAL_REGISTER, 0x00 << 24); in add_card()
[all …]
/linux/drivers/media/tuners/
H A Dqm1d1c0042.c64 static int reg_write(struct qm1d1c0042_state *state, u8 reg, u8 val) in reg_write() function
107 return reg_write(state, 0x03, state->regs[0x03]); in qm1d1c0042_set_srch_mode()
117 ret = reg_write(state, 0x01, state->regs[0x01]); in qm1d1c0042_wakeup()
119 ret = reg_write(state, 0x05, state->regs[0x05]); in qm1d1c0042_wakeup()
205 ret = reg_write(state, 0x02, val); in qm1d1c0042_set_params()
213 ret = reg_write(state, 0x06, state->regs[0x06]); in qm1d1c0042_set_params()
219 ret = reg_write(state, 0x07, state->regs[0x07]); in qm1d1c0042_set_params()
230 ret = reg_write(state, 0x08, val); in qm1d1c0042_set_params()
251 ret = reg_write(state, 0x09, state->regs[0x09]); in qm1d1c0042_set_params()
253 ret = reg_write(state, 0x0a, state->regs[0x0a]); in qm1d1c0042_set_params()
[all …]
H A Dmxl301rf.c45 static int reg_write(struct mxl301rf_state *state, u8 reg, u8 val) in reg_write() function
83 ret = reg_write(state, 0x14, 0x01); in mxl301rf_get_rf_strength()
215 ret = reg_write(state, 0x1a, 0x0d); in mxl301rf_set_params()
259 ret = reg_write(state, 0x01, 0x01); in mxl301rf_init()
/linux/drivers/media/usb/gspca/
H A Dspca505.c533 static int reg_write(struct gspca_dev *gspca_dev, in reg_write() function
577 ret = reg_write(gspca_dev, data[i][0], data[i][2], in write_vector()
619 reg_write(gspca_dev, 0x05, 0x00, (255 - brightness) >> 6); in setbrightness()
620 reg_write(gspca_dev, 0x05, 0x01, (255 - brightness) << 2); in setbrightness()
651 ret = reg_write(gspca_dev, 0x06, 0x16, 0x0a); in sd_start()
654 reg_write(gspca_dev, 0x05, 0xc2, 0x12); in sd_start()
659 reg_write(gspca_dev, 0x02, 0x00, 0x00); in sd_start()
662 reg_write(gspca_dev, SPCA50X_REG_COMPRESS, 0x00, mode_tb[mode][0]); in sd_start()
663 reg_write(gspca_dev, SPCA50X_REG_COMPRESS, 0x06, mode_tb[mode][1]); in sd_start()
664 reg_write(gspca_dev, SPCA50X_REG_COMPRESS, 0x07, mode_tb[mode][2]); in sd_start()
[all …]
H A Dspca508.c1231 static int reg_write(struct gspca_dev *gspca_dev, u16 index, u16 value) in reg_write() function
1278 ret = reg_write(gspca_dev, 0x8802, reg >> 8); in ssi_w()
1281 ret = reg_write(gspca_dev, 0x8801, reg & 0x00ff); in ssi_w()
1285 ret = reg_write(gspca_dev, 0x8805, val & 0x00ff); in ssi_w()
1290 ret = reg_write(gspca_dev, 0x8800, val); in ssi_w()
1325 ret = reg_write(gspca_dev, (*data)[1], in write_vector()
1393 reg_write(gspca_dev, 0x8500, mode); in sd_start()
1397 reg_write(gspca_dev, 0x8700, 0x28); /* clock */ in sd_start()
1402 reg_write(gspca_dev, 0x8700, 0x23); /* clock */ in sd_start()
1405 reg_write(gspca_dev, 0x8112, 0x10 | 0x20); in sd_start()
[all …]
H A Dspca501.c1745 static int reg_write(struct gspca_dev *gspca_dev, in reg_write() function
1769 ret = reg_write(gspca_dev, data[i][0], data[i][2], in write_vector()
1783 reg_write(gspca_dev, SPCA501_REG_CCDSP, 0x12, val); in setbrightness()
1788 reg_write(gspca_dev, 0x00, 0x00, (val >> 8) & 0xff); in setcontrast()
1789 reg_write(gspca_dev, 0x00, 0x01, val & 0xff); in setcontrast()
1794 reg_write(gspca_dev, SPCA501_REG_CCDSP, 0x0c, val); in setcolors()
1799 reg_write(gspca_dev, SPCA501_REG_CCDSP, 0x11, val); in setblue_balance()
1804 reg_write(gspca_dev, SPCA501_REG_CCDSP, 0x13, val); in setred_balance()
1880 reg_write(gspca_dev, SPCA50X_REG_USB, 0x6, 0x94); in sd_start()
1883 reg_write(gspca_dev, SPCA50X_REG_USB, 0x07, 0x004a); in sd_start()
[all …]
/linux/drivers/gpu/drm/bridge/
H A Dtda998x_drv.c652 reg_write(struct tda998x_priv *priv, u16 reg, u8 val) in reg_write() function
696 reg_write(priv, reg, old_val | val); in reg_set()
706 reg_write(priv, reg, old_val & ~val); in reg_clear()
713 reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER); in tda998x_reset()
715 reg_write(priv, REG_SOFTRESET, 0); in tda998x_reset()
723 reg_write(priv, REG_PLL_SERIAL_1, 0x00); in tda998x_reset()
724 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1)); in tda998x_reset()
725 reg_write(priv, REG_PLL_SERIAL_3, 0x00); in tda998x_reset()
726 reg_write(priv, REG_SERIALIZER, 0x00); in tda998x_reset()
727 reg_write(priv, REG_BUFFER_OUT, 0x00); in tda998x_reset()
[all …]
/linux/drivers/media/platform/st/stm32/dma2d/
H A Ddma2d-hw.c24 static inline void reg_write(void __iomem *base, u32 reg, u32 val) in reg_write() function
32 reg_write(base, reg, (reg_read(base, reg) & ~mask) | val); in reg_update_bits()
49 reg_write(d->regs, DMA2D_IFCR_REG, isr_val & 0x003f); in dma2d_clear_int()
58 reg_write(d->regs, DMA2D_NLR_REG, (width << 16) | height); in dma2d_config_common()
75 reg_write(d->regs, DMA2D_OMAR_REG, o_addr); in dma2d_config_out()
77 reg_write(d->regs, DMA2D_OCOLR_REG, in dma2d_config_out()
90 reg_write(d->regs, DMA2D_FGMAR_REG, f_addr); in dma2d_config_fg()
105 reg_write(d->regs, DMA2D_FGCOLR_REG, in dma2d_config_fg()
114 reg_write(d->regs, DMA2D_BGMAR_REG, b_addr); in dma2d_config_bg()
129 reg_write(d->regs, DMA2D_BGCOLR_REG, in dma2d_config_bg()
/linux/drivers/media/pci/tw686x/
H A Dtw686x-core.c108 reg_write(dev, DMA_CHANNEL_ENABLE, dma_en); in tw686x_disable_channel()
109 reg_write(dev, DMA_CMD, dma_cmd); in tw686x_disable_channel()
133 reg_write(dev, DMA_CHANNEL_ENABLE, dev->pending_dma_en); in tw686x_dma_delay()
134 reg_write(dev, DMA_CMD, dev->pending_dma_cmd); in tw686x_dma_delay()
156 reg_write(dev, DMA_CHANNEL_ENABLE, dma_en & ~ch_mask); in tw686x_reset_channels()
162 reg_write(dev, DMA_CMD, dma_cmd & ~ch_mask); in tw686x_reset_channels()
300 reg_write(dev, SYS_SOFT_RST, 0x0f); in tw686x_probe()
303 reg_write(dev, SRST[0], 0x3f); in tw686x_probe()
305 reg_write(dev, SRST[1], 0x3f); in tw686x_probe()
308 reg_write(dev, DMA_CMD, 0); in tw686x_probe()
[all …]
H A Dtw686x-audio.c74 reg_write(dev, reg, next->dma); in tw686x_audio_irq()
159 reg_write(dev, AUDIO_CONTROL2, reg); in tw686x_pcm_prepare()
170 reg_write(dev, AUDIO_CONTROL1, reg); in tw686x_pcm_prepare()
198 reg_write(dev, ADMA_P_ADDR[ac->ch], p_buf->dma); in tw686x_pcm_prepare()
199 reg_write(dev, ADMA_B_ADDR[ac->ch], b_buf->dma); in tw686x_pcm_prepare()
338 reg_write(dev, reg, ac->dma_descs[pb].phys); in tw686x_audio_dma_alloc()
352 reg_write(dev, DMA_CMD, dma_cmd & ~0xff00); in tw686x_audio_free()
353 reg_write(dev, DMA_CHANNEL_ENABLE, dma_ch_mask & ~0xff00); in tw686x_audio_free()
369 reg_write(dev, AUDIO_CONTROL1, BIT(0)); in tw686x_audio_init()
/linux/drivers/soundwire/
H A Dqcom.c221 int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val); member
505 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_WR_CMD], val); in qcom_swrm_cmd_fifo_wr_cmd()
545 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD], val); in qcom_swrm_cmd_fifo_rd_cmd()
562 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, in qcom_swrm_cmd_fifo_rd_cmd()
564 ctrl->reg_write(ctrl, in qcom_swrm_cmd_fifo_rd_cmd()
764 ctrl->reg_write(ctrl, in qcom_swrm_irq_handler()
791 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1); in qcom_swrm_irq_handler()
800 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1); in qcom_swrm_irq_handler()
807 ctrl->reg_write(ctrl, in qcom_swrm_irq_handler()
817 ctrl->reg_write(ctrl, in qcom_swrm_irq_handler()
[all …]
/linux/drivers/i3c/master/mipi-i3c-hci/
H A Dhci_quirks.c29 reg_write(HCI_SCL_I3C_OD_TIMING, AMD_SCL_I3C_OD_TIMING); in amd_set_od_pp_timing()
30 reg_write(HCI_SCL_I3C_PP_TIMING, AMD_SCL_I3C_PP_TIMING); in amd_set_od_pp_timing()
34 reg_write(HCI_SDA_HOLD_SWITCH_DLY_TIMING, data); in amd_set_od_pp_timing()
43 reg_write(QUEUE_THLD_CTRL, data); in amd_set_resp_buf_thld()
H A Dcore.c133 reg_write(MASTER_DEVICE_ADDR, in i3c_hci_bus_init()
175 reg_write(RESET_CONTROL, RX_FIFO_RST | TX_FIFO_RST | RESP_QUEUE_RST); in mipi_i3c_hci_pio_reset()
181 reg_write(DCT_SECTION, FIELD_PREP(DCT_TABLE_INDEX, 0)); in mipi_i3c_hci_dct_index_reset()
539 reg_write(INTR_STATUS, val); in i3c_hci_irq_handler()
643 reg_write(RESET_CONTROL, SOFT_RST); in i3c_hci_init()
650 reg_write(INTR_SIGNAL_ENABLE, 0x0); in i3c_hci_init()
656 reg_write(INTR_STATUS_ENABLE, GENMASK(31, 10)); in i3c_hci_init()
663 reg_write(HC_CONTROL, regval); in i3c_hci_init()
673 reg_write(HC_CONTROL, regval); in i3c_hci_init()
/linux/drivers/iio/dac/
H A Dad5592r-base.c55 return st->ops->reg_write(st, AD5592R_REG_GPIO_SET, st->gpio_val); in ad5592r_gpio_set()
68 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_OUT_EN, st->gpio_out); in ad5592r_gpio_direction_input()
72 return st->ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in); in ad5592r_gpio_direction_input()
91 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_SET, st->gpio_val); in ad5592r_gpio_direction_output()
95 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_OUT_EN, st->gpio_out); in ad5592r_gpio_direction_output()
99 return st->ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in); in ad5592r_gpio_direction_output()
164 st->ops->reg_write(st, AD5592R_REG_RESET, 0xdac); in ad5592r_reset()
242 ret = ops->reg_write(st, AD5592R_REG_PULLDOWN, pulldown); in ad5592r_set_channel_modes()
246 ret = ops->reg_write(st, AD5592R_REG_TRISTATE, tristate); in ad5592r_set_channel_modes()
251 ret = ops->reg_write(st, AD5592R_REG_DAC_EN, dac); in ad5592r_set_channel_modes()
[all …]
/linux/drivers/watchdog/
H A Dstm32_iwdg.c92 static inline void reg_write(void __iomem *base, u32 reg, u32 val) in reg_write() function
122 reg_write(wdt->regs, IWDG_KR, KR_KEY_EWA); in stm32_iwdg_start()
125 reg_write(wdt->regs, IWDG_PR, iwdg_pr); in stm32_iwdg_start()
126 reg_write(wdt->regs, IWDG_RLR, iwdg_rlr); in stm32_iwdg_start()
128 reg_write(wdt->regs, IWDG_EWCR, iwdg_ewcr | EWCR_EWIE); in stm32_iwdg_start()
129 reg_write(wdt->regs, IWDG_KR, KR_KEY_ENABLE); in stm32_iwdg_start()
141 reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD); in stm32_iwdg_start()
153 reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD); in stm32_iwdg_ping()
192 reg_write(wdt->regs, IWDG_EWCR, reg); in stm32_iwdg_isr()
/linux/drivers/base/regmap/
H A Dregmap-fsi.c36 .reg_write = regmap_fsi32_reg_write,
61 .reg_write = regmap_fsi32le_reg_write,
90 .reg_write = regmap_fsi16_reg_write,
119 .reg_write = regmap_fsi16le_reg_write,
148 .reg_write = regmap_fsi8_reg_write,
H A Dregmap-w1.c177 .reg_write = w1_reg_a8_v8_write,
182 .reg_write = w1_reg_a8_v16_write,
187 .reg_write = w1_reg_a16_v16_write,
H A Dregmap-mdio.c41 .reg_write = regmap_mdio_c22_write,
81 .reg_write = regmap_mdio_c45_write,
/linux/drivers/media/i2c/
H A Dak881x.c40 static int reg_write(struct i2c_client *client, const u8 reg, in reg_write() function
52 return reg_write(client, reg, (ret & ~mask) | (data & mask)); in reg_set()
86 if (reg_write(client, reg->reg, reg->val) < 0) in ak881x_s_register()
191 reg_write(client, AK881X_DAC_MODE, dac); in ak881x_s_stream()
196 reg_write(client, AK881X_DAC_MODE, 0); in ak881x_s_stream()
287 reg_write(client, AK881X_INTERFACE_MODE, ifmode | (20 << 3)); in ak881x_probe()
/linux/drivers/i2c/busses/
H A Di2c-pasemi-core.c63 static inline void reg_write(struct pasemi_smbus *smbus, int reg, int val) in reg_write() function
77 #define TXFIFO_WR(smbus, reg) reg_write((smbus), REG_MTXFIFO, (reg))
87 reg_write(smbus, REG_CTL, val); in pasemi_reset()
117 reg_write(smbus, REG_SMSTA, status); in pasemi_smb_clear()
128 reg_write(smbus, REG_IMASK, SMSTA_XEN | SMSTA_MTN); in pasemi_smb_waitready()
132 reg_write(smbus, REG_IMASK, 0); in pasemi_smb_waitready()
188 reg_write(smbus, REG_SMSTA, SMSTA_XEN); in pasemi_smb_waitready()
441 reg_write(smbus, REG_IMASK, 0); in pasemi_i2c_common_probe()
457 reg_write(smbus, REG_IMASK, 0); in pasemi_irq_handler()
/linux/drivers/net/wireless/broadcom/brcm80211/brcmfmac/
H A Dbtcoex.c108 } reg_write; in brcmf_btcoex_params_write() local
110 reg_write.addr = cpu_to_le32(addr); in brcmf_btcoex_params_write()
111 reg_write.data = cpu_to_le32(data); in brcmf_btcoex_params_write()
113 &reg_write, sizeof(reg_write)); in brcmf_btcoex_params_write()
/linux/drivers/media/dvb-frontends/
H A Dtc90522.c46 reg_write(struct tc90522_state *state, const struct reg_val *regs, int num) in reg_write() function
107 return reg_write(fe->demodulator_priv, set_tsid, ARRAY_SIZE(set_tsid)); in tc90522s_set_tsid()
119 return reg_write(fe->demodulator_priv, &rv, 1); in tc90522t_set_layers()
495 ret = reg_write(state, &reset_sat, 1); in tc90522_set_frontend()
500 ret = reg_write(state, &reset_ter, 1); in tc90522_set_frontend()
559 return reg_write(state, rv, num); in tc90522_set_if_agc()
572 ret = reg_write(state, &sleep_sat, 1); in tc90522_sleep()
574 ret = reg_write(state, &sleep_ter, 1); in tc90522_sleep()
605 ret = reg_write(state, &wakeup_sat, 1); in tc90522_init()
607 ret = reg_write(state, &wakeup_ter, 1); in tc90522_init()
/linux/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_reg.c86 srv->funcs.reg_write(srv->user_ctx, addr, reg_val); in dmub_reg_update()
101 srv->funcs.reg_write(srv->user_ctx, addr, reg_val); in dmub_reg_set()

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