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Searched refs:reg_val (Results 1 – 25 of 185) sorted by relevance

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/linux/drivers/media/dvb-frontends/
H A Daf9033_priv.h19 struct reg_val { struct
87 static const struct reg_val ofsm_init[] = {
202 static const struct reg_val tuner_init_tua9001[] = {
246 static const struct reg_val tuner_init_fc0011[] = {
309 static const struct reg_val tuner_init_fc0012[] = {
354 static const struct reg_val tuner_init_mxl5007t[] = {
391 static const struct reg_val tuner_init_tda18218[] = {
427 static const struct reg_val tuner_init_fc2580[] = {
467 static const struct reg_val ofsm_init_it9135_v1[] = {
582 static const struct reg_val tuner_init_it9135_38[] = {
[all …]
/linux/arch/riscv/kvm/
H A Dvcpu_onereg.c43 unsigned long reg_val; in kvm_riscv_vcpu_get_reg_config() local
50 reg_val = vcpu->arch.isa[0] & KVM_RISCV_BASE_ISA_MASK; in kvm_riscv_vcpu_get_reg_config()
55 reg_val = riscv_cbom_block_size; in kvm_riscv_vcpu_get_reg_config()
60 reg_val = riscv_cboz_block_size; in kvm_riscv_vcpu_get_reg_config()
65 reg_val = riscv_cbop_block_size; in kvm_riscv_vcpu_get_reg_config()
68 reg_val = vcpu->arch.mvendorid; in kvm_riscv_vcpu_get_reg_config()
71 reg_val = vcpu->arch.marchid; in kvm_riscv_vcpu_get_reg_config()
74 reg_val = vcpu->arch.mimpid; in kvm_riscv_vcpu_get_reg_config()
77 reg_val = satp_mode >> SATP_MODE_SHIFT; in kvm_riscv_vcpu_get_reg_config()
83 if (copy_to_user(uaddr, &reg_val, KVM_REG_SIZE(reg->id))) in kvm_riscv_vcpu_get_reg_config()
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H A Dvcpu_sbi.c220 unsigned long reg_val) in riscv_vcpu_set_sbi_ext_single() argument
225 if (reg_val != 1 && reg_val != 0) in riscv_vcpu_set_sbi_ext_single()
232 scontext->ext_status[sext->ext_idx] = (reg_val) ? in riscv_vcpu_set_sbi_ext_single()
241 unsigned long *reg_val) in riscv_vcpu_get_sbi_ext_single() argument
250 *reg_val = scontext->ext_status[sext->ext_idx] == in riscv_vcpu_get_sbi_ext_single()
258 unsigned long reg_val, bool enable) in riscv_vcpu_set_sbi_ext_multi() argument
265 for_each_set_bit(i, &reg_val, BITS_PER_LONG) { in riscv_vcpu_set_sbi_ext_multi()
278 unsigned long *reg_val) in riscv_vcpu_get_sbi_ext_multi() argument
293 *reg_val |= KVM_REG_RISCV_SBI_MULTI_MASK(ext_id); in riscv_vcpu_get_sbi_ext_multi()
332 unsigned long reg_val, reg_subtype; in kvm_riscv_vcpu_set_reg_sbi_ext() local
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H A Dvcpu_fp.c89 void *reg_val; in kvm_riscv_vcpu_get_reg_fp() local
96 reg_val = &cntx->fp.f.fcsr; in kvm_riscv_vcpu_get_reg_fp()
101 reg_val = &cntx->fp.f.f[reg_num]; in kvm_riscv_vcpu_get_reg_fp()
109 reg_val = &cntx->fp.d.fcsr; in kvm_riscv_vcpu_get_reg_fp()
116 reg_val = &cntx->fp.d.f[reg_num]; in kvm_riscv_vcpu_get_reg_fp()
122 if (copy_to_user(uaddr, reg_val, KVM_REG_SIZE(reg->id))) in kvm_riscv_vcpu_get_reg_fp()
138 void *reg_val; in kvm_riscv_vcpu_set_reg_fp() local
145 reg_val = &cntx->fp.f.fcsr; in kvm_riscv_vcpu_set_reg_fp()
150 reg_val = &cntx->fp.f.f[reg_num]; in kvm_riscv_vcpu_set_reg_fp()
158 reg_val = &cntx->fp.d.fcsr; in kvm_riscv_vcpu_set_reg_fp()
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/linux/sound/drivers/opl3/
H A Dopl3_synth.c394 unsigned char reg_val; in snd_opl3_play_note() local
414 reg_val = (unsigned char) note->fnum; in snd_opl3_play_note()
416 opl3->command(opl3, opl3_reg, reg_val); in snd_opl3_play_note()
418 reg_val = 0x00; in snd_opl3_play_note()
421 reg_val |= OPL3_KEYON_BIT; in snd_opl3_play_note()
423 reg_val |= (note->octave << 2) & OPL3_BLOCKNUM_MASK; in snd_opl3_play_note()
425 reg_val |= (unsigned char) (note->fnum >> 8) & OPL3_FNUM_HIGH_MASK; in snd_opl3_play_note()
429 opl3->command(opl3, opl3_reg, reg_val); in snd_opl3_play_note()
442 unsigned char reg_val; in snd_opl3_set_voice() local
468 reg_val = 0x00; in snd_opl3_set_voice()
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/linux/drivers/net/ethernet/allwinner/
H A Dsun4i-emac.c105 unsigned int reg_val; in emac_update_speed() local
108 reg_val = readl(db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed()
109 reg_val &= ~EMAC_MAC_SUPP_100M; in emac_update_speed()
111 reg_val |= EMAC_MAC_SUPP_100M; in emac_update_speed()
112 writel(reg_val, db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed()
118 unsigned int reg_val; in emac_update_duplex() local
121 reg_val = readl(db->membase + EMAC_MAC_CTL1_REG); in emac_update_duplex()
122 reg_val &= ~EMAC_MAC_CTL1_DUPLEX_EN; in emac_update_duplex()
124 reg_val |= EMAC_MAC_CTL1_DUPLEX_EN; in emac_update_duplex()
125 writel(reg_val, db->membase + EMAC_MAC_CTL1_REG); in emac_update_duplex()
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/linux/arch/arm/mach-qcom/
H A Dplatsmp.c84 u32 reg_val; in cortex_a7_release_secondary() local
103 reg_val = CORE_RST | COREPOR_RST | CLAMP | CORE_MEM_CLAMP; in cortex_a7_release_secondary()
104 writel(reg_val, reg + APCS_CPU_PWR_CTL); in cortex_a7_release_secondary()
111 reg_val &= ~CORE_MEM_CLAMP; in cortex_a7_release_secondary()
112 writel(reg_val, reg + APCS_CPU_PWR_CTL); in cortex_a7_release_secondary()
113 reg_val |= L2DT_SLP; in cortex_a7_release_secondary()
114 writel(reg_val, reg + APCS_CPU_PWR_CTL); in cortex_a7_release_secondary()
117 reg_val = (reg_val | BIT(17)) & ~CLAMP; in cortex_a7_release_secondary()
118 writel(reg_val, reg + APCS_CPU_PWR_CTL); in cortex_a7_release_secondary()
122 reg_val &= ~(CORE_RST | COREPOR_RST); in cortex_a7_release_secondary()
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/linux/arch/powerpc/platforms/powernv/
H A Dopal-fadump.h83 __be64 reg_val; member
88 u64 reg_val) in opal_fadump_set_regval_regnum() argument
92 regs->gpr[reg_num] = reg_val; in opal_fadump_set_regval_regnum()
98 regs->ctr = reg_val; in opal_fadump_set_regval_regnum()
101 regs->link = reg_val; in opal_fadump_set_regval_regnum()
104 regs->xer = reg_val; in opal_fadump_set_regval_regnum()
107 regs->dar = reg_val; in opal_fadump_set_regval_regnum()
110 regs->dsisr = reg_val; in opal_fadump_set_regval_regnum()
113 regs->nip = reg_val; in opal_fadump_set_regval_regnum()
116 regs->msr = reg_val; in opal_fadump_set_regval_regnum()
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/linux/drivers/gpu/drm/msm/hdmi/
H A Dhdmi_hdcp.c45 u32 reg_val; member
199 u32 reg_val, hdcp_int_status; in msm_hdmi_hdcp_irq() local
203 reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_INT_CTRL); in msm_hdmi_hdcp_irq()
204 hdcp_int_status = reg_val & HDCP_INT_STATUS_MASK; in msm_hdmi_hdcp_irq()
210 reg_val |= hdcp_int_status << 1; in msm_hdmi_hdcp_irq()
213 reg_val |= HDMI_HDCP_INT_CTRL_AUTH_FAIL_INFO_ACK; in msm_hdmi_hdcp_irq()
214 hdmi_write(hdmi, REG_HDMI_HDCP_INT_CTRL, reg_val); in msm_hdmi_hdcp_irq()
228 reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_LINK0_STATUS); in msm_hdmi_hdcp_irq()
230 __func__, reg_val); in msm_hdmi_hdcp_irq()
284 u32 reg_val, failure, nack0; in msm_reset_hdcp_ddc_failures() local
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/linux/arch/mips/pci/
H A Dfixup-malta.c70 unsigned char reg_val; in malta_piix_func0_fixup() local
84 pci_read_config_byte(pdev, PIIX4_FUNC0_PIRQRC+i, &reg_val); in malta_piix_func0_fixup()
85 if (reg_val & PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE) in malta_piix_func0_fixup()
88 pci_irq[PCIA+i] = piixirqmap[reg_val & in malta_piix_func0_fixup()
98 pci_read_config_byte(pdev, PIIX4_FUNC0_TOM, &reg_val); in malta_piix_func0_fixup()
99 pci_write_config_byte(pdev, PIIX4_FUNC0_TOM, reg_val | in malta_piix_func0_fixup()
109 pci_read_config_byte(pdev, PIIX4_FUNC0_SERIRQC, &reg_val); in malta_piix_func0_fixup()
110 reg_val |= PIIX4_FUNC0_SERIRQC_EN | PIIX4_FUNC0_SERIRQC_CONT; in malta_piix_func0_fixup()
111 pci_write_config_byte(pdev, PIIX4_FUNC0_SERIRQC, reg_val); in malta_piix_func0_fixup()
124 unsigned char reg_val; in malta_piix_func1_fixup() local
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/linux/drivers/net/ethernet/cavium/liquidio/
H A Dcn23xx_vf_device.c68 u64 reg_val = octeon_read_csr64(oct, in cn23xx_vf_reset_io_queues() local
70 while ((READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_RST) && in cn23xx_vf_reset_io_queues()
71 !(READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_QUIET) && in cn23xx_vf_reset_io_queues()
73 WRITE_ONCE(reg_val, octeon_read_csr64( in cn23xx_vf_reset_io_queues()
83 WRITE_ONCE(reg_val, READ_ONCE(reg_val) & in cn23xx_vf_reset_io_queues()
86 READ_ONCE(reg_val)); in cn23xx_vf_reset_io_queues()
88 WRITE_ONCE(reg_val, octeon_read_csr64( in cn23xx_vf_reset_io_queues()
90 if (READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_RST) { in cn23xx_vf_reset_io_queues()
153 u32 reg_val; in cn23xx_vf_setup_global_output_regs() local
160 reg_val = in cn23xx_vf_setup_global_output_regs()
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H A Dcn23xx_pf_device.c136 u64 reg_val; in cn23xx_setup_global_mac_regs() local
145 reg_val = in cn23xx_setup_global_mac_regs()
150 reg_val = pf_num * CN23XX_MAX_RINGS_PER_PF_PASS_1_1; in cn23xx_setup_global_mac_regs()
153 reg_val = pf_num * CN23XX_MAX_RINGS_PER_PF; in cn23xx_setup_global_mac_regs()
157 reg_val = reg_val | in cn23xx_setup_global_mac_regs()
161 reg_val |= (temp << CN23XX_PKT_MAC_CTL_RINFO_RPVF_BIT_POS); in cn23xx_setup_global_mac_regs()
165 reg_val |= (temp << CN23XX_PKT_MAC_CTL_RINFO_NVFS_BIT_POS); in cn23xx_setup_global_mac_regs()
169 reg_val); in cn23xx_setup_global_mac_regs()
199 u64 reg_val = octeon_read_csr64(oct, in cn23xx_reset_io_queues() local
201 while ((READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_RST) && in cn23xx_reset_io_queues()
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/linux/drivers/power/supply/
H A Dintel_dc_ti_battery.c132 unsigned int reg_val; in dc_ti_battery_get_voltage_and_current_now() local
165 ret = regmap_read(chip->regmap, DC_TI_CC_ACC0_REG, &reg_val); in dc_ti_battery_get_voltage_and_current_now()
169 acc = reg_val; in dc_ti_battery_get_voltage_and_current_now()
171 ret = regmap_read(chip->regmap, DC_TI_CC_ACC1_REG, &reg_val); in dc_ti_battery_get_voltage_and_current_now()
175 acc |= reg_val << 8; in dc_ti_battery_get_voltage_and_current_now()
177 ret = regmap_read(chip->regmap, DC_TI_CC_ACC2_REG, &reg_val); in dc_ti_battery_get_voltage_and_current_now()
181 acc |= reg_val << 16; in dc_ti_battery_get_voltage_and_current_now()
183 ret = regmap_read(chip->regmap, DC_TI_CC_ACC3_REG, &reg_val); in dc_ti_battery_get_voltage_and_current_now()
187 acc |= reg_val << 24; in dc_ti_battery_get_voltage_and_current_now()
190 ret = regmap_read(chip->regmap, DC_TI_SMPL_CTR0_REG, &reg_val); in dc_ti_battery_get_voltage_and_current_now()
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H A Dmax1720x_battery.c366 unsigned int reg_val; in max1720x_battery_get_property() local
371 ret = max172xx_battery_health(info, &reg_val); in max1720x_battery_get_property()
372 val->intval = reg_val; in max1720x_battery_get_property()
380 ret = regmap_read(info->regmap, MAX172XX_STATUS, &reg_val); in max1720x_battery_get_property()
386 val->intval = !FIELD_GET(MAX172XX_STATUS_BAT_ABSENT, reg_val); in max1720x_battery_get_property()
389 ret = regmap_read(info->regmap, MAX172XX_REPSOC, &reg_val); in max1720x_battery_get_property()
390 val->intval = max172xx_percent_to_ps(reg_val); in max1720x_battery_get_property()
393 ret = regmap_read(info->regmap, MAX172XX_BATT, &reg_val); in max1720x_battery_get_property()
394 val->intval = max172xx_voltage_to_ps(reg_val); in max1720x_battery_get_property()
397 ret = regmap_read(info->regmap, MAX172XX_DESIGN_CAP, &reg_val); in max1720x_battery_get_property()
[all …]
/linux/sound/soc/codecs/aw88395/
H A Daw88395_device.c190 int reg_val; in aw_dev_read_chipid()
193 ret = regmap_read(aw_dev->regmap, AW88395_CHIP_ID_REG, &reg_val); in aw_dev_read_chipid()
199 dev_info(aw_dev->dev, "chip id = %x\n", reg_val); in aw_dev_read_chipid()
200 *chip_id = reg_val; in aw_dev_read_chipid()
452 unsigned int reg_val; in aw_dev_dsp_check_st()
457 ret = regmap_read(aw_dev->regmap, AW88395_SYSST_REG, &reg_val); in aw_dev_dsp_check_st()
463 if ((reg_val & (~AW88395_DSPS_MASK)) != AW88395_DSPS_NORMAL_VALUE) { in aw_dev_dsp_check_st()
464 dev_err(aw_dev->dev, "check dsp st fail,reg_val:0x%04x", reg_val); in aw_dev_dsp_check_st()
468 dev_dbg(aw_dev->dev, "dsp st check ok, reg_val in aw_dev_dsp_check_st()
189 int reg_val; aw_dev_read_chipid() local
451 unsigned int reg_val; aw_dev_dsp_check_st() local
575 unsigned int reg_val; aw_dev_get_icalk() local
595 unsigned int reg_val; aw_dev_get_vcalk() local
617 unsigned int reg_val; aw_dev_get_vcalk_dac() local
662 u32 vcalb_adj, reg_val; aw_dev_set_vcalb() local
757 unsigned int reg_val; aw_dev_get_int_status() local
783 unsigned int reg_val; aw_dev_get_iis_status() local
816 unsigned int reg_val; aw_dev_check_mode2_pll() local
884 unsigned int reg_val; aw_dev_check_sysst() local
908 u16 reg_val; aw_dev_check_sysint() local
923 unsigned int reg_val; aw_dev_get_cur_mode_st() local
939 unsigned int reg_val = 0; aw_dev_get_dsp_config() local
980 unsigned int reg_val; aw_dev_get_dsp_status() local
1005 u16 reg_val; aw_dev_update_reg_container() local
1126 __be16 reg_val; aw_dev_dsp_update_container() local
1231 unsigned int reg_val; aw_dev_check_sram() local
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/linux/arch/x86/hyperv/
H A Dhv_apic.c39 u64 reg_val; in hv_apic_icr_read() local
41 rdmsrq(HV_X64_MSR_ICR, reg_val); in hv_apic_icr_read()
42 return reg_val; in hv_apic_icr_read()
47 u64 reg_val; in hv_apic_icr_write() local
49 reg_val = SET_XAPIC_DEST_FIELD(id); in hv_apic_icr_write()
50 reg_val = reg_val << 32; in hv_apic_icr_write()
51 reg_val |= low; in hv_apic_icr_write()
53 wrmsrq(HV_X64_MSR_ICR, reg_val); in hv_apic_icr_write()
63 u32 reg_val, hi; in hv_apic_read() local
67 rdmsr(HV_X64_MSR_EOI, reg_val, hi); in hv_apic_read()
[all …]
/linux/drivers/edac/
H A Ddmc520_edac.c255 u32 reg_val = readl(reg_base + REG_OFFSET_FEATURE_CONFIG); in dmc520_is_ecc_enabled() local
257 return FIELD_GET(REG_FIELD_DRAM_ECC_ENABLED, reg_val); in dmc520_is_ecc_enabled()
263 u32 reg_val, scrub_cfg; in dmc520_get_scrub_type() local
265 reg_val = dmc520_read_reg(pvt, REG_OFFSET_SCRUB_CONTROL0_NOW); in dmc520_get_scrub_type()
266 scrub_cfg = FIELD_GET(SCRUB_TRIGGER0_NEXT_MASK, reg_val); in dmc520_get_scrub_type()
280 u32 reg_val; in dmc520_get_memory_width() local
282 reg_val = dmc520_read_reg(pvt, REG_OFFSET_FORMAT_CONTROL); in dmc520_get_memory_width()
283 mem_width_field = FIELD_GET(MEMORY_WIDTH_MASK, reg_val); in dmc520_get_memory_width()
296 u32 reg_val; in dmc520_get_mtype() local
298 reg_val = dmc520_read_reg(pvt, REG_OFFSET_MEMORY_TYPE_NOW); in dmc520_get_mtype()
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/linux/drivers/mtd/nand/raw/
H A Domap_elm.c106 u32 reg_val; in elm_config() local
124 reg_val = (bch_type & ECC_BCH_LEVEL_MASK) | (ELM_ECC_SIZE << 16); in elm_config()
125 elm_write_reg(info, ELM_LOCATION_CONFIG, reg_val); in elm_config()
145 u32 reg_val; in elm_configure_page_mode() local
147 reg_val = elm_read_reg(info, ELM_PAGE_CTRL); in elm_configure_page_mode()
149 reg_val |= BIT(index); /* enable page mode */ in elm_configure_page_mode()
151 reg_val &= ~BIT(index); /* disable page mode */ in elm_configure_page_mode()
153 elm_write_reg(info, ELM_PAGE_CTRL, reg_val); in elm_configure_page_mode()
254 u32 reg_val; in elm_start_processing() local
264 reg_val = elm_read_reg(info, offset); in elm_start_processing()
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/linux/drivers/iio/adc/
H A Dmt6370-adc.c70 unsigned int reg_val; in mt6370_adc_read_channel() local
76 reg_val = MT6370_ADC_START_MASK | in mt6370_adc_read_channel()
78 ret = regmap_write(priv->regmap, MT6370_REG_CHG_ADC, reg_val); in mt6370_adc_read_channel()
85 MT6370_REG_CHG_ADC, reg_val, in mt6370_adc_read_channel()
86 !(reg_val & MT6370_ADC_START_MASK), in mt6370_adc_read_channel()
135 unsigned int reg_val; in mt6370_adc_read_scale() local
145 ret = regmap_read(priv->regmap, MT6370_REG_CHG_CTRL3, &reg_val); in mt6370_adc_read_scale()
149 reg_val = FIELD_GET(MT6370_AICR_ICHG_MASK, reg_val); in mt6370_adc_read_scale()
150 switch (reg_val) { in mt6370_adc_read_scale()
168 ret = regmap_read(priv->regmap, MT6370_REG_CHG_CTRL7, &reg_val); in mt6370_adc_read_scale()
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/linux/drivers/mfd/
H A Dadp5520.c75 uint8_t reg_val; in __adp5520_ack_bits() local
80 ret = __adp5520_read(client, reg, &reg_val); in __adp5520_ack_bits()
83 reg_val |= bit_mask; in __adp5520_ack_bits()
84 ret = __adp5520_write(client, reg, reg_val); in __adp5520_ack_bits()
106 uint8_t reg_val; in adp5520_set_bits() local
111 ret = __adp5520_read(chip->client, reg, &reg_val); in adp5520_set_bits()
113 if (!ret && ((reg_val & bit_mask) != bit_mask)) { in adp5520_set_bits()
114 reg_val |= bit_mask; in adp5520_set_bits()
115 ret = __adp5520_write(chip->client, reg, reg_val); in adp5520_set_bits()
126 uint8_t reg_val; in adp5520_clr_bits() local
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/linux/drivers/clk/bcm/
H A Dclk-kona.c35 static inline u32 bitfield_extract(u32 reg_val, u32 shift, u32 width) in bitfield_extract() argument
37 return (reg_val & bitfield_mask(shift, width)) >> shift; in bitfield_extract()
41 static inline u32 bitfield_replace(u32 reg_val, u32 shift, u32 width, u32 val) in bitfield_replace() argument
45 return (reg_val & ~mask) | (val << shift); in bitfield_replace()
112 __ccu_write(struct ccu_data *ccu, u32 reg_offset, u32 reg_val) in __ccu_write() argument
114 writel(reg_val, ccu->base + reg_offset); in __ccu_write()
312 u32 reg_val; in policy_init() local
314 reg_val = __ccu_read(ccu, offset); in policy_init()
315 reg_val |= mask; in policy_init()
316 __ccu_write(ccu, offset, reg_val); in policy_init()
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/linux/sound/soc/amd/acp/
H A Dacp-i2s.c201 u32 reg_val, fmt_reg, tdm_fmt; in acp_i2s_hwparams() local
229 reg_val = ACP_BTTDM_ITER; in acp_i2s_hwparams()
233 reg_val = ACP_I2STDM_ITER; in acp_i2s_hwparams()
237 reg_val = ACP_HSTDM_ITER; in acp_i2s_hwparams()
248 reg_val = ACP_BTTDM_IRER; in acp_i2s_hwparams()
252 reg_val = ACP_I2STDM_IRER; in acp_i2s_hwparams()
256 reg_val = ACP_HSTDM_IRER; in acp_i2s_hwparams()
266 val = readl(chip->base + reg_val); in acp_i2s_hwparams()
269 writel(val, chip->base + reg_val); in acp_i2s_hwparams()
272 val = readl(chip->base + reg_val); in acp_i2s_hwparams()
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/linux/sound/soc/kirkwood/
H A Dkirkwood-i2s.c57 u32 reg_val; in armada_38x_i2s_init_quirk() local
69 reg_val = readl(priv->soc_control); in armada_38x_i2s_init_quirk()
71 reg_val |= A38X_SPDIF_MODE_ENABLE; in armada_38x_i2s_init_quirk()
74 reg_val &= ~A38X_SPDIF_MODE_ENABLE; in armada_38x_i2s_init_quirk()
77 writel(reg_val, priv->soc_control); in armada_38x_i2s_init_quirk()
90 u32 reg_val; in armada_38x_set_pll() local
95 reg_val = readl(base + A38X_PLL_CONF_REG1); in armada_38x_set_pll()
96 reg_val &= ~A38X_PLL_FREQ_OFFSET_VALID; in armada_38x_set_pll()
97 reg_val &= ~A38X_PLL_SW_RESET; in armada_38x_set_pll()
98 writel(reg_val, base + A38X_PLL_CONF_REG1); in armada_38x_set_pll()
[all …]
/linux/drivers/net/ethernet/samsung/sxgbe/
H A Dsxgbe_dma.c23 u32 reg_val; in sxgbe_dma_init() local
25 reg_val = readl(ioaddr + SXGBE_DMA_SYSBUS_MODE_REG); in sxgbe_dma_init()
33 reg_val |= SXGBE_DMA_AXI_UNDEF_BURST; in sxgbe_dma_init()
36 reg_val |= (burst_map << SXGBE_DMA_BLENMAP_LSHIFT); in sxgbe_dma_init()
38 writel(reg_val, ioaddr + SXGBE_DMA_SYSBUS_MODE_REG); in sxgbe_dma_init()
47 u32 reg_val; in sxgbe_dma_channel_init() local
50 reg_val = readl(ioaddr + SXGBE_DMA_CHA_CTL_REG(cha_num)); in sxgbe_dma_channel_init()
53 reg_val |= SXGBE_DMA_PBL_X8MODE; in sxgbe_dma_channel_init()
54 writel(reg_val, ioaddr + SXGBE_DMA_CHA_CTL_REG(cha_num)); in sxgbe_dma_channel_init()
56 reg_val = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num)); in sxgbe_dma_channel_init()
[all …]
/linux/drivers/net/phy/mscc/
H A Dmscc_serdes.c96 u32 reg_val; in vsc85xx_sd6g_des_cfg_wr() local
100 reg_val = (des_phy_ctrl << PHY_S6G_DES_PHY_CTRL_POS) | in vsc85xx_sd6g_des_cfg_wr()
107 reg_val); in vsc85xx_sd6g_des_cfg_wr()
120 u32 reg_val; in vsc85xx_sd6g_ib_cfg0_wr() local
126 reg_val = base_val | (ib_rtrm_adj << 25) | in vsc85xx_sd6g_ib_cfg0_wr()
132 reg_val); in vsc85xx_sd6g_ib_cfg0_wr()
146 u32 reg_val = 0; in vsc85xx_sd6g_ib_cfg1_wr() local
152 reg_val = (ib_tjtag << 17) + (ib_tsdet << 12) + (ib_scaly << 8) + in vsc85xx_sd6g_ib_cfg1_wr()
156 reg_val); in vsc85xx_sd6g_ib_cfg1_wr()
190 u32 reg_val; in vsc85xx_sd6g_ib_cfg3_wr() local
[all …]

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