Searched refs:reg_table (Results 1 – 5 of 5) sorted by relevance
519 } reg_table[] = { variable584 for (i = 0; i < ARRAY_SIZE(reg_table); i++) { in mshv_vtl_get_set_reg()585 if (reg_table[i].reg_name != gpr_name) in mshv_vtl_get_set_reg()587 if (reg_table[i].debug_reg_num != -1) { in mshv_vtl_get_set_reg()593 native_set_debugreg(reg_table[i].debug_reg_num, *reg64); in mshv_vtl_get_set_reg()595 *reg64 = native_get_debugreg(reg_table[i].debug_reg_num); in mshv_vtl_get_set_reg()599 wrmsrl(reg_table[i].msr_addr, *reg64); in mshv_vtl_get_set_reg()601 rdmsrl(reg_table[i].msr_addr, *reg64); in mshv_vtl_get_set_reg()
264 static const struct reg_table { struct
291 const struct reg_table *t; in mt7601u_load_bbp_temp_table_bw()303 const struct reg_table *t; in mt7601u_bbp_temp()
3975 struct atom_mc_reg_table *reg_table) in radeon_atom_init_mc_reg_table() argument3983 memset(reg_table, 0, sizeof(struct atom_mc_reg_table)); in radeon_atom_init_mc_reg_table()4012 reg_table->mc_reg_address[i].s1 = in radeon_atom_init_mc_reg_table()4014 reg_table->mc_reg_address[i].pre_reg_data = in radeon_atom_init_mc_reg_table()4020 reg_table->last = i; in radeon_atom_init_mc_reg_table()4026 reg_table->mc_reg_table_entry[num_ranges].mclk_max = in radeon_atom_init_mc_reg_table()4029 for (i = 0, j = 1; i < reg_table->last; i++) { in radeon_atom_init_mc_reg_table()4030 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) { in radeon_atom_init_mc_reg_table()4031 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] = in radeon_atom_init_mc_reg_table()4034 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) { in radeon_atom_init_mc_reg_table()[all …]
840 const struct drm_i915_reg_descriptor *reg_table, in check_sorted() argument848 u32 curr = i915_mmio_reg_offset(reg_table[i].addr); in check_sorted()