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Searched refs:reg_off (Results 1 – 25 of 76) sorted by relevance

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/linux/tools/testing/selftests/kvm/riscv/
H A Dget-reg-list.c192 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CONFIG); in config_id_to_str() local
196 switch (reg_off) { in config_id_to_str()
213 return strdup_printf("%lld /* UNKNOWN */", reg_off); in config_id_to_str()
219 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CORE); in core_id_to_str() local
223 switch (reg_off) { in core_id_to_str()
236 reg_off - KVM_REG_RISCV_CORE_REG(regs.t0)); in core_id_to_str()
239 reg_off - KVM_REG_RISCV_CORE_REG(regs.s0)); in core_id_to_str()
242 reg_off - KVM_REG_RISCV_CORE_REG(regs.a0)); in core_id_to_str()
245 reg_off - KVM_REG_RISCV_CORE_REG(regs.s2) + 2); in core_id_to_str()
248 reg_off - KVM_REG_RISCV_CORE_REG(regs.t3) + 3); in core_id_to_str()
[all …]
/linux/drivers/mmc/host/
H A Dcavium.h37 #define MIO_EMM_CFG(x) (0x00 + x->reg_off)
38 #define MIO_EMM_SWITCH(x) (0x48 + x->reg_off)
39 #define MIO_EMM_DMA(x) (0x50 + x->reg_off)
40 #define MIO_EMM_CMD(x) (0x58 + x->reg_off)
41 #define MIO_EMM_RSP_STS(x) (0x60 + x->reg_off)
42 #define MIO_EMM_RSP_LO(x) (0x68 + x->reg_off)
43 #define MIO_EMM_RSP_HI(x) (0x70 + x->reg_off)
44 #define MIO_EMM_INT(x) (0x78 + x->reg_off)
45 #define MIO_EMM_INT_EN(x) (0x80 + x->reg_off)
46 #define MIO_EMM_WDOG(x) (0x88 + x->reg_off)
[all …]
/linux/drivers/clk/meson/
H A Ds4-pll.c30 .reg_off = ANACTRL_FIXPLL_CTRL0,
35 .reg_off = ANACTRL_FIXPLL_CTRL0,
40 .reg_off = ANACTRL_FIXPLL_CTRL1,
45 .reg_off = ANACTRL_FIXPLL_CTRL0,
50 .reg_off = ANACTRL_FIXPLL_CTRL0,
55 .reg_off = ANACTRL_FIXPLL_CTRL0,
269 .reg_off = ANACTRL_GP0PLL_CTRL0,
274 .reg_off = ANACTRL_GP0PLL_CTRL0,
279 .reg_off = ANACTRL_GP0PLL_CTRL0,
284 .reg_off = ANACTRL_GP0PLL_CTRL0,
[all …]
H A Da1-pll.c22 .reg_off = ANACTRL_FIXPLL_CTRL0,
27 .reg_off = ANACTRL_FIXPLL_CTRL0,
32 .reg_off = ANACTRL_FIXPLL_CTRL0,
37 .reg_off = ANACTRL_FIXPLL_CTRL1,
42 .reg_off = ANACTRL_FIXPLL_STS,
47 .reg_off = ANACTRL_FIXPLL_CTRL0,
93 .reg_off = ANACTRL_HIFIPLL_CTRL0,
98 .reg_off = ANACTRL_HIFIPLL_CTRL0,
103 .reg_off = ANACTRL_HIFIPLL_CTRL0,
108 .reg_off = ANACTRL_HIFIPLL_CTRL1,
[all …]
H A Daxg.c29 .reg_off = HHI_MPLL_CNTL,
34 .reg_off = HHI_MPLL_CNTL,
39 .reg_off = HHI_MPLL_CNTL,
44 .reg_off = HHI_MPLL_CNTL2,
49 .reg_off = HHI_MPLL_CNTL,
54 .reg_off = HHI_MPLL_CNTL,
93 .reg_off = HHI_SYS_PLL_CNTL,
98 .reg_off = HHI_SYS_PLL_CNTL,
103 .reg_off = HHI_SYS_PLL_CNTL,
108 .reg_off = HHI_SYS_PLL_CNTL,
[all …]
H A Dc3-pll.c249 .reg_off = ANACTRL_GP0PLL_CTRL0,
254 .reg_off = ANACTRL_GP0PLL_CTRL0,
259 .reg_off = ANACTRL_GP0PLL_CTRL1,
264 .reg_off = ANACTRL_GP0PLL_CTRL0,
269 .reg_off = ANACTRL_GP0PLL_CTRL0,
274 .reg_off = ANACTRL_GP0PLL_CTRL0,
332 .reg_off = ANACTRL_HIFIPLL_CTRL0,
337 .reg_off = ANACTRL_HIFIPLL_CTRL0,
342 .reg_off = ANACTRL_HIFIPLL_CTRL1,
347 .reg_off = ANACTRL_HIFIPLL_CTRL0,
[all …]
H A Dg12a-aoclk.c124 .reg_off = AO_RTC_ALT_CLK_CNTL0,
129 .reg_off = AO_RTC_ALT_CLK_CNTL0,
134 .reg_off = AO_RTC_ALT_CLK_CNTL1,
139 .reg_off = AO_RTC_ALT_CLK_CNTL1,
144 .reg_off = AO_RTC_ALT_CLK_CNTL0,
215 .reg_off = AO_CEC_CLK_CNTL_REG0,
220 .reg_off = AO_CEC_CLK_CNTL_REG0,
225 .reg_off = AO_CEC_CLK_CNTL_REG1,
230 .reg_off = AO_CEC_CLK_CNTL_REG1,
235 .reg_off = AO_CEC_CLK_CNTL_REG0,
H A Dmeson8-ddr.c28 .reg_off = AM_DDR_PLL_CNTL,
33 .reg_off = AM_DDR_PLL_CNTL,
38 .reg_off = AM_DDR_PLL_CNTL,
43 .reg_off = AM_DDR_PLL_CNTL,
48 .reg_off = AM_DDR_PLL_CNTL,
H A Dgxbb.c89 .reg_off = HHI_MPLL_CNTL,
94 .reg_off = HHI_MPLL_CNTL,
99 .reg_off = HHI_MPLL_CNTL,
104 .reg_off = HHI_MPLL_CNTL2,
109 .reg_off = HHI_MPLL_CNTL,
114 .reg_off = HHI_MPLL_CNTL,
166 .reg_off = HHI_HDMI_PLL_CNTL,
171 .reg_off = HHI_HDMI_PLL_CNTL,
176 .reg_off = HHI_HDMI_PLL_CNTL,
181 .reg_off = HHI_HDMI_PLL_CNTL2,
[all …]
H A Dparm.h25 u16 reg_off; member
34 regmap_read(map, p->reg_off, &val); in meson_parm_read()
41 regmap_update_bits(map, p->reg_off, SETPMASK(p->width, p->shift), in meson_parm_write()
H A Dg12a.c34 .reg_off = HHI_FIX_PLL_CNTL0,
39 .reg_off = HHI_FIX_PLL_CNTL0,
44 .reg_off = HHI_FIX_PLL_CNTL0,
49 .reg_off = HHI_FIX_PLL_CNTL1,
54 .reg_off = HHI_FIX_PLL_CNTL0,
59 .reg_off = HHI_FIX_PLL_CNTL0,
103 .reg_off = HHI_SYS_PLL_CNTL0,
108 .reg_off = HHI_SYS_PLL_CNTL0,
113 .reg_off = HHI_SYS_PLL_CNTL0,
118 .reg_off = HHI_SYS_PLL_CNTL0,
[all …]
/linux/drivers/pinctrl/sunplus/
H A Dsppctl.c112 static inline u32 sppctl_get_reg_and_bit_offset(unsigned int offset, u32 *reg_off) in sppctl_get_reg_and_bit_offset() argument
117 *reg_off = (offset / 32) * 4; in sppctl_get_reg_and_bit_offset()
123 static inline u32 sppctl_get_moon_reg_and_bit_offset(unsigned int offset, u32 *reg_off) in sppctl_get_moon_reg_and_bit_offset() argument
133 *reg_off = (offset / 16) * 4; in sppctl_get_moon_reg_and_bit_offset()
139 static inline u32 sppctl_prep_moon_reg_and_offset(unsigned int offset, u32 *reg_off, int val) in sppctl_prep_moon_reg_and_offset() argument
143 bit_off = sppctl_get_moon_reg_and_bit_offset(offset, reg_off); in sppctl_prep_moon_reg_and_offset()
227 static void sppctl_gmx_set(struct sppctl_pdata *pctl, u8 reg_off, u8 bit_off, u8 bit_sz, in sppctl_gmx_set() argument
240 writel(reg, pctl->moon1_base + reg_off * 4); in sppctl_gmx_set()
264 u32 reg_off, bit_off, reg; in sppctl_first_get() local
266 bit_off = sppctl_get_reg_and_bit_offset(offset, &reg_off); in sppctl_first_get()
[all …]
/linux/drivers/pinctrl/
H A Dpinctrl-digicolor.c130 int bit_off, reg_off; in dc_set_mux() local
133 dc_client_sel(group, &reg_off, &bit_off); in dc_set_mux()
135 reg = readb_relaxed(pmap->regs + reg_off); in dc_set_mux()
138 writeb_relaxed(reg, pmap->regs + reg_off); in dc_set_mux()
148 int bit_off, reg_off; in dc_pmx_request_gpio() local
151 dc_client_sel(offset, &reg_off, &bit_off); in dc_pmx_request_gpio()
153 reg = readb_relaxed(pmap->regs + reg_off); in dc_pmx_request_gpio()
171 int reg_off = GP_DRIVE0(gpio/PINS_PER_COLLECTION); in dc_gpio_direction_input() local
177 drive = readb_relaxed(pmap->regs + reg_off); in dc_gpio_direction_input()
179 writeb_relaxed(drive, pmap->regs + reg_off); in dc_gpio_direction_input()
[all …]
/linux/sound/soc/tegra/
H A Dtegra210_mbdrc.c787 u32 reg_off = i * TEGRA210_MBDRC_FILTER_PARAM_STRIDE; in tegra210_mbdrc_hw_params() local
790 reg_off + TEGRA210_MBDRC_CFG_RAM_CTRL, in tegra210_mbdrc_hw_params()
791 reg_off + TEGRA210_MBDRC_CFG_RAM_DATA, in tegra210_mbdrc_hw_params()
849 u32 reg_off = i * TEGRA210_MBDRC_FILTER_PARAM_STRIDE; in tegra210_mbdrc_component_init() local
852 reg_off + TEGRA210_MBDRC_IIR_CFG, in tegra210_mbdrc_component_init()
858 reg_off + TEGRA210_MBDRC_IN_ATTACK, in tegra210_mbdrc_component_init()
864 reg_off + TEGRA210_MBDRC_IN_RELEASE, in tegra210_mbdrc_component_init()
870 reg_off + TEGRA210_MBDRC_FAST_ATTACK, in tegra210_mbdrc_component_init()
889 reg_off + TEGRA210_MBDRC_IN_THRESHOLD, in tegra210_mbdrc_component_init()
906 reg_off + TEGRA210_MBDRC_OUT_THRESHOLD, in tegra210_mbdrc_component_init()
[all …]
/linux/drivers/net/ethernet/marvell/octeon_ep_vf/
H A Doctep_vf_main.h305 #define octep_vf_write_csr(octep_vf_dev, reg_off, value) \ argument
306 writel(value, (octep_vf_dev)->mmio.hw_addr + (reg_off))
308 #define octep_vf_write_csr64(octep_vf_dev, reg_off, val64) \ argument
309 writeq(val64, (octep_vf_dev)->mmio.hw_addr + (reg_off))
311 #define octep_vf_read_csr(octep_vf_dev, reg_off) \ argument
312 readl((octep_vf_dev)->mmio.hw_addr + (reg_off))
314 #define octep_vf_read_csr64(octep_vf_dev, reg_off) \ argument
315 readq((octep_vf_dev)->mmio.hw_addr + (reg_off))
/linux/drivers/gpu/drm/msm/disp/dpu1/catalog/
H A Ddpu_4_1_sdm670.h16 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
17 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
18 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
19 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
20 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
H A Ddpu_7_0_sm8350.h25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
26 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
29 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
30 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
33 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
34 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
H A Ddpu_6_0_sm8250.h25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
26 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
29 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
30 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
33 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
34 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
H A Ddpu_8_1_sm8450.h26 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
30 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
33 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
34 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
35 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
H A Ddpu_5_0_sm8150.h28 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
30 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
31 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
32 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
33 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
34 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
35 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
36 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
H A Ddpu_6_4_sm6350.h25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
26 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
27 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
28 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
29 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
30 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
H A Ddpu_5_1_sc8180x.h28 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
30 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
31 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
32 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
33 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
34 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
35 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
36 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
H A Ddpu_3_2_sdm660.h27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
29 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
30 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
32 [DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 },
/linux/drivers/pinctrl/realtek/
H A Dpinctrl-rtd.c290 u32 pulsel_off, pulen_off, smt_off, curr_off, pow_off, reg_off, p_off, n_off; in rtd_pconf_parse_conf() local
307 reg_off = config_desc->reg_offset; in rtd_pconf_parse_conf()
320 reg_off = config_desc->reg_offset; in rtd_pconf_parse_conf()
332 reg_off = config_desc->reg_offset; in rtd_pconf_parse_conf()
345 reg_off = config_desc->reg_offset; in rtd_pconf_parse_conf()
358 reg_off = config_desc->reg_offset; in rtd_pconf_parse_conf()
366 reg_off = config_desc->reg_offset; in rtd_pconf_parse_conf()
400 reg_off = config_desc->reg_offset; in rtd_pconf_parse_conf()
403 reg_off += 0x4; in rtd_pconf_parse_conf()
418 reg_off = sconfig_desc->reg_offset; in rtd_pconf_parse_conf()
[all …]
/linux/drivers/net/ethernet/marvell/octeon_ep/
H A Doctep_main.h336 #define octep_write_csr(octep_dev, reg_off, value) \ argument
337 writel(value, (octep_dev)->mmio[0].hw_addr + (reg_off))
339 #define octep_write_csr64(octep_dev, reg_off, val64) \ argument
340 writeq(val64, (octep_dev)->mmio[0].hw_addr + (reg_off))
342 #define octep_read_csr(octep_dev, reg_off) \ argument
343 readl((octep_dev)->mmio[0].hw_addr + (reg_off))
345 #define octep_read_csr64(octep_dev, reg_off) \ argument
346 readq((octep_dev)->mmio[0].hw_addr + (reg_off))

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