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Searched refs:regSDMA0_UTCL1_WR_STATUS_BASE_IDX (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/sdma/
H A Dsdma_4_4_0_offset.h112 #define regSDMA0_UTCL1_WR_STATUS_BASE_IDX … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_5_0_offset.h111 #define regSDMA0_UTCL1_WR_STATUS_BASE_IDX … macro
H A Dgc_12_0_0_offset.h103 #define regSDMA0_UTCL1_WR_STATUS_BASE_IDX … macro
H A Dgc_11_0_3_offset.h109 #define regSDMA0_UTCL1_WR_STATUS_BASE_IDX … macro
H A Dgc_11_0_0_offset.h109 #define regSDMA0_UTCL1_WR_STATUS_BASE_IDX … macro