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Searched refs:regPWRSEQ1_BL_PWM_GRP1_REG_LOCK_BASE_IDX (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_3_1_4_offset.h7209 #define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK_BASE_IDX … macro
H A Ddpcs_4_2_3_offset.h131 #define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK_BASE_IDX … macro
H A Ddpcs_4_2_2_offset.h114 #define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK_BASE_IDX … macro
H A Ddpcs_4_2_0_offset.h127 #define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK_BASE_IDX … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_5_offset.h12331 #define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h10453 #define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h10474 #define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h11575 #define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h12466 #define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h13062 #define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK_BASE_IDX … macro