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Searched refs:regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h8262 #define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h8875 #define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h6894 #define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h6915 #define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h8167 #define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h9116 #define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h8261 #define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h9340 #define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h8918 #define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX … macro