Home
last modified time | relevance | path

Searched refs:regOTG0_OTG_V_TOTAL_MID_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h7924 #define regOTG0_OTG_V_TOTAL_MID_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h8537 #define regOTG0_OTG_V_TOTAL_MID_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h6528 #define regOTG0_OTG_V_TOTAL_MID_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h6549 #define regOTG0_OTG_V_TOTAL_MID_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h7829 #define regOTG0_OTG_V_TOTAL_MID_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h8774 #define regOTG0_OTG_V_TOTAL_MID_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h7923 #define regOTG0_OTG_V_TOTAL_MID_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h8998 #define regOTG0_OTG_V_TOTAL_MID_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h8546 #define regOTG0_OTG_V_TOTAL_MID_BASE_IDX … macro