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Searched refs:regNBIF_SDP_VWR_VCHG_RST_CTRL0_BASE_IDX (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_9_0_offset.h6183 #define regNBIF_SDP_VWR_VCHG_RST_CTRL0_BASE_IDX 8 macro
H A Dnbio_4_3_0_offset.h13795 #define regNBIF_SDP_VWR_VCHG_RST_CTRL0_BASE_IDX … macro
H A Dnbio_7_7_0_offset.h6717 #define regNBIF_SDP_VWR_VCHG_RST_CTRL0_BASE_IDX … macro
H A Dnbio_7_2_0_offset.h7487 #define regNBIF_SDP_VWR_VCHG_RST_CTRL0_BASE_IDX … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/nbif/
H A Dnbif_6_3_1_offset.h7480 #define regNBIF_SDP_VWR_VCHG_RST_CTRL0_BASE_IDX … macro