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Searched refs:regDSCL3_SCL_TAP_CONTROL_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h4470 #define regDSCL3_SCL_TAP_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h5609 #define regDSCL3_SCL_TAP_CONTROL_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h5739 #define regDSCL3_SCL_TAP_CONTROL_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h5760 #define regDSCL3_SCL_TAP_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h6759 #define regDSCL3_SCL_TAP_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h5850 #define regDSCL3_SCL_TAP_CONTROL_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h4469 #define regDSCL3_SCL_TAP_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h6070 #define regDSCL3_SCL_TAP_CONTROL_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h4901 #define regDSCL3_SCL_TAP_CONTROL_BASE_IDX … macro