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Searched refs:regDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h4076 #define regDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h4913 #define regDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h5323 #define regDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h5344 #define regDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h6063 #define regDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h5154 #define regDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h4075 #define regDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h5374 #define regDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h4388 #define regDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX … macro