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Searched refs:regDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h4134 #define regDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h4971 #define regDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h5381 #define regDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h5402 #define regDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h6121 #define regDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h5212 #define regDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h4133 #define regDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h5432 #define regDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h4446 #define regDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX … macro