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Searched refs:regDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h3686 #define regDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h4221 #define regDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h4911 #define regDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h4932 #define regDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h5371 #define regDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h4462 #define regDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h3685 #define regDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h4682 #define regDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h3878 #define regDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX … macro