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Searched refs:regDP4_DP_MSA_TIMING_PARAM1 (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h10073 #define regDP4_DP_MSA_TIMING_PARAM1 … macro
H A Ddcn_3_1_5_offset.h10660 #define regDP4_DP_MSA_TIMING_PARAM1 … macro
H A Ddcn_3_5_1_offset.h9682 #define regDP4_DP_MSA_TIMING_PARAM1 … macro
H A Ddcn_3_5_0_offset.h9703 #define regDP4_DP_MSA_TIMING_PARAM1 … macro
H A Ddcn_3_1_4_offset.h10824 #define regDP4_DP_MSA_TIMING_PARAM1 … macro
H A Ddcn_3_1_2_offset.h10905 #define regDP4_DP_MSA_TIMING_PARAM1 … macro
H A Ddcn_3_2_1_offset.h10072 #define regDP4_DP_MSA_TIMING_PARAM1 … macro
H A Ddcn_3_1_6_offset.h11129 #define regDP4_DP_MSA_TIMING_PARAM1 … macro