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Searched refs:regCP_MES_IC_OP_CNTL (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmes_v11_0.c1071 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); in mes_v11_0_load_microcode()
1074 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); in mes_v11_0_load_microcode()
1077 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); in mes_v11_0_load_microcode()
1079 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); in mes_v11_0_load_microcode()
H A Dmes_v12_0.c1230 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); in mes_v12_0_load_microcode()
1233 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); in mes_v12_0_load_microcode()
1236 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); in mes_v12_0_load_microcode()
1238 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); in mes_v12_0_load_microcode()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_12_0_0_offset.h4684 #define regCP_MES_IC_OP_CNTL … macro
H A Dgc_11_0_3_offset.h7800 #define regCP_MES_IC_OP_CNTL … macro
H A Dgc_11_0_0_offset.h7494 #define regCP_MES_IC_OP_CNTL … macro