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Searched refs:regCP_MES_IC_OP_CNTL (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmes_v11_0.c1510 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); in mes_v11_0_mqd_init()
1513 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); in mes_v11_0_mqd_init()
1516 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); in mes_v11_0_mqd_init()
1518 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data);
H A Dmes_v12_1.c1179 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_OP_CNTL); in mes_v12_1_load_microcode()
1182 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_OP_CNTL, data); in mes_v12_1_load_microcode()
1185 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_OP_CNTL); in mes_v12_1_load_microcode()
1187 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_OP_CNTL, data); in mes_v12_1_load_microcode()
H A Dmes_v12_0.c1590 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); in mes_v12_0_mqd_init()
1593 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); in mes_v12_0_mqd_init()
1596 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); in mes_v12_0_queue_init_register()
1598 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); in mes_v12_0_queue_init_register()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_12_0_0_offset.h4684 #define regCP_MES_IC_OP_CNTL … macro
H A Dgc_11_0_3_offset.h7800 #define regCP_MES_IC_OP_CNTL … macro
H A Dgc_11_0_0_offset.h7494 #define regCP_MES_IC_OP_CNTL … macro