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Searched refs:regCP_MES_CNTL (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmes_v11_0.c1270 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); in mes_v11_0_enable()
1274 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); in mes_v11_0_enable()
1297 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); in mes_v11_0_enable()
1304 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); in mes_v11_0_enable()
1313 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); in mes_v11_0_enable()
H A Dmes_v12_1.c1080 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL); in mes_v12_1_enable()
1083 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL, data); in mes_v12_1_enable()
1104 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL, data); in mes_v12_1_enable()
1113 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL); in mes_v12_1_enable()
1121 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL, data); in mes_v12_1_enable()
H A Dmes_v12_0.c1328 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); in mes_v12_0_enable()
1333 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); in mes_v12_0_enable()
1347 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); in mes_v12_0_enable()
1360 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); in mes_v12_0_enable()
1368 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); in mes_v12_0_enable()
H A Dgfx_v12_1.c119 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL),
H A Dgfx_v12_0.c131 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL),
H A Dgfx_v11_0.c196 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL),
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_12_0_0_offset.h4634 #define regCP_MES_CNTL … macro
H A Dgc_11_0_3_offset.h7750 #define regCP_MES_CNTL … macro
H A Dgc_11_0_0_offset.h7444 #define regCP_MES_CNTL … macro