Searched refs:regCP_MEC_RS64_CNTL (Results 1 – 6 of 6) sorted by relevance
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | gfx_v12_0.c | 2186 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); in gfx_v12_0_config_gfx_rs64()
2191 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); in gfx_v12_0_config_gfx_rs64()
2198 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); in gfx_v12_0_config_gfx_rs64()
2789 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); in gfx_v12_0_cp_compute_enable()
2810 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); in gfx_v12_0_cp_compute_enable()
5370 reset_pipe = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); in gfx_v12_0_reset_compute_pipe()
5402 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, reset_pipe); in gfx_v12_0_reset_compute_pipe()
5403 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, clean_pipe); in gfx_v12_0_reset_compute_pipe()
|
| H A D | gfx_v11_0.c | 3048 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); in gfx_v11_0_config_gfx_rs64()
3053 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
3060 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
3850 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); in gfx_v11_0_cp_compute_enable()
3871 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); in gfx_v11_0_cp_compute_enable()
5168 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, 0x0); in gfx_v11_0_soft_reset()
6936 reset_pipe = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); in gfx_v11_0_reset_compute_pipe()
6969 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, reset_pipe); in gfx_v11_0_reset_compute_pipe()
6970 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, clean_pipe); in gfx_v11_0_reset_compute_pipe()
|
| H A D | gfx_v12_1.c | 1806 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL); in gfx_v12_1_xcc_config_gfx_rs64()
1811 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL, tmp); in gfx_v12_1_xcc_config_gfx_rs64()
1818 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL, tmp); in gfx_v12_1_xcc_config_gfx_rs64()
1902 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL); in gfx_v12_1_xcc_cp_compute_enable()
1923 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL, data); in gfx_v12_1_xcc_cp_compute_enable()
|
| /linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_12_0_0_offset.h | 4952 #define regCP_MEC_RS64_CNTL … macro
|
| H A D | gc_11_0_3_offset.h | 8066 #define regCP_MEC_RS64_CNTL … macro
|
| H A D | gc_11_0_0_offset.h | 7762 #define regCP_MEC_RS64_CNTL … macro
|