Home
last modified time | relevance | path

Searched refs:regCP_MEC_CNTL (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmes_v11_0.c535 reset_val = RREG32_SOC15(GC, 0, regCP_MEC_CNTL); in mes_v11_0_reset_compute_pipe_mmio()
599 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, reset_val); in mes_v11_0_reset_compute_pipe_mmio()
601 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, clean_val); in mes_v11_0_reset_compute_pipe_mmio()
H A Dmes_v12_0.c551 reset_val = RREG32_SOC15(GC, 0, regCP_MEC_CNTL); in mes_v12_0_reset_compute_pipe_mmio()
571 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, reset_val); in mes_v12_0_reset_compute_pipe_mmio()
574 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, clean_val); in mes_v12_0_reset_compute_pipe_mmio()
H A Dgfx_v9_4_3.c93 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL),
1669 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 0); in gfx_v9_4_3_xcc_cp_compute_enable()
1671 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, in gfx_v9_4_3_xcc_cp_compute_enable()
3621 reset_pipe = RREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL); in gfx_v9_4_3_reset_hw_pipe()
3654 WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL, reset_pipe); in gfx_v9_4_3_reset_hw_pipe()
3655 WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL, clean_pipe); in gfx_v9_4_3_reset_hw_pipe()
H A Dgfx_v11_0.c195 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL),
3917 data = RREG32_SOC15(GC, 0, regCP_MEC_CNTL); in gfx_v11_0_cp_compute_enable()
3928 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, data); in gfx_v11_0_cp_compute_enable()
H A Dgfx_v12_1.c118 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL),
H A Dgfx_v12_0.c130 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL),
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h142 #define regCP_MEC_CNTL … macro
H A Dgc_9_4_2_offset.h185 #define regCP_MEC_CNTL … macro
H A Dgc_12_0_0_offset.h4056 #define regCP_MEC_CNTL … macro
H A Dgc_11_0_3_offset.h6476 #define regCP_MEC_CNTL … macro
H A Dgc_11_0_0_offset.h6196 #define regCP_MEC_CNTL … macro