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Searched refs:regCP_MEC_CNTL (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v11_0.c174 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL),
3841 data = RREG32_SOC15(GC, 0, regCP_MEC_CNTL); in gfx_v11_0_cp_compute_enable()
3852 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, data); in gfx_v11_0_cp_compute_enable()
6970 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, reset_pipe); in gfx_v11_0_reset_compute_pipe()
6971 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, clean_pipe); in gfx_v11_0_reset_compute_pipe()
H A Dgfx_v12_0.c130 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL),
5396 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, reset_pipe); in gfx_v12_0_reset_compute_pipe()
5397 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, clean_pipe); in gfx_v12_0_reset_compute_pipe()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h142 #define regCP_MEC_CNTL … macro
H A Dgc_9_4_2_offset.h185 #define regCP_MEC_CNTL … macro
H A Dgc_12_0_0_offset.h4056 #define regCP_MEC_CNTL … macro
H A Dgc_11_0_3_offset.h6476 #define regCP_MEC_CNTL … macro
H A Dgc_11_0_0_offset.h6196 #define regCP_MEC_CNTL … macro