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Searched refs:regCP_HQD_PQ_BASE (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmes_v11_0.c1549 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); in mes_v11_0_queue_init_register()
H A Dmes_v12_1.c1402 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); in mes_v12_1_queue_init_register()
H A Dmes_v12_0.c1625 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); in mes_v12_0_queue_init_register()
H A Dgfx_v9_4_3.c122 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE),
1947 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE, in gfx_v9_4_3_xcc_kiq_init_register()
H A Dgfx_v12_1.c148 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE),
2634 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE, in gfx_v12_1_xcc_kiq_init_register()
H A Dgfx_v12_0.c162 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE),
3376 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, in gfx_v12_0_kiq_init_register()
H A Dgfx_v11_0.c228 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE),
4536 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, in gfx_v11_0_kiq_init_register()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h3298 #define regCP_HQD_PQ_BASE … macro
H A Dgc_9_4_2_offset.h709 #define regCP_HQD_PQ_BASE … macro
H A Dgc_12_0_0_offset.h3858 #define regCP_HQD_PQ_BASE … macro
H A Dgc_11_0_3_offset.h4840 #define regCP_HQD_PQ_BASE … macro
H A Dgc_11_0_0_offset.h4616 #define regCP_HQD_PQ_BASE … macro