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Searched refs:regCP_HQD_EOP_BASE_ADDR (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_4_3.c134 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR),
1905 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR, in gfx_v9_4_3_xcc_kiq_init_register()
H A Dgfx_v12_1.c160 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR),
2592 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR, in gfx_v12_1_xcc_kiq_init_register()
H A Dgfx_v12_0.c174 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR),
3336 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR, in gfx_v12_0_kiq_init_register()
H A Dgfx_v11_0.c240 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR),
4496 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR, in gfx_v11_0_kiq_init_register()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h3360 #define regCP_HQD_EOP_BASE_ADDR … macro
H A Dgc_9_4_2_offset.h771 #define regCP_HQD_EOP_BASE_ADDR … macro
H A Dgc_12_0_0_offset.h3918 #define regCP_HQD_EOP_BASE_ADDR … macro
H A Dgc_11_0_3_offset.h4902 #define regCP_HQD_EOP_BASE_ADDR … macro
H A Dgc_11_0_0_offset.h4678 #define regCP_HQD_EOP_BASE_ADDR … macro