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Searched refs:regCP_CPC_IC_BASE_CNTL (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v11_0.c2720 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2724 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); in gfx_v11_0_config_pfp_cache_rs64()
2990 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); in gfx_v11_0_config_mec_cache_rs64()
2994 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); in gfx_v11_0_config_mec_cache_rs64()
4089 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); in gfx_v11_0_cp_compute_load_microcode_rs64()
4093 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); in gfx_v11_0_cp_compute_load_microcode_rs64()
H A Dgfx_v12_1.c2141 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL); in gfx_v12_1_config_gfx_rs64()
2145 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp); in gfx_v12_1_config_gfx_rs64()
H A Dgfx_v12_0.c2914 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); in gfx_v12_0_cp_compute_load_microcode_rs64()
2918 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); in gfx_v12_0_cp_compute_load_microcode_rs64()
H A Dgfx_v9_4_3.c1714 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp); in gfx_v9_4_3_xcc_cp_compute_load_microcode()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h3046 #define regCP_CPC_IC_BASE_CNTL … macro
H A Dgc_9_4_2_offset.h585 #define regCP_CPC_IC_BASE_CNTL … macro
H A Dgc_12_0_0_offset.h6216 #define regCP_CPC_IC_BASE_CNTL … macro
H A Dgc_11_0_3_offset.h10290 #define regCP_CPC_IC_BASE_CNTL … macro
H A Dgc_11_0_0_offset.h9740 #define regCP_CPC_IC_BASE_CNTL … macro