Searched refs:regCC_RB_BACKEND_DISABLE (Results 1 – 9 of 9) sorted by relevance
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | imu_v11_0.c | 213 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_RB_BACKEND_DISABLE, 0x0fffff01, 0xe0000000),
284 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_RB_BACKEND_DISABLE, 0x00000f01, 0xe0000000),
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| H A D | imu_v11_0_3.c | 59 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_RB_BACKEND_DISABLE, 0xffffff01, 0xe0000000),
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| H A D | gfx_v12_0.c | 1711 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); in gfx_v12_0_get_rb_active_bitmap()
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| H A D | gfx_v11_0.c | 1997 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); in gfx_v11_0_get_rb_active_bitmap()
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| /linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_9_4_3_offset.h | 1046 #define regCC_RB_BACKEND_DISABLE … macro
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| H A D | gc_9_4_2_offset.h | 4758 #define regCC_RB_BACKEND_DISABLE … macro
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| H A D | gc_12_0_0_offset.h | 7587 #define regCC_RB_BACKEND_DISABLE … macro
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| H A D | gc_11_0_3_offset.h | 2496 #define regCC_RB_BACKEND_DISABLE … macro
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| H A D | gc_11_0_0_offset.h | 2388 #define regCC_RB_BACKEND_DISABLE … macro
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