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Searched refs:ref_dtbclk_khz (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
H A Ddcn35_clk_mgr.c258 int ref_dtbclk_khz) in dcn35_update_clocks_update_dtb_dto() argument
274 dto_params.ref_dtbclk_khz = ref_dtbclk_khz; in dcn35_update_clocks_update_dtb_dto()
409 if (new_clocks->dtbclk_en && !new_clocks->ref_dtbclk_khz) in dcn35_update_clocks()
410 new_clocks->ref_dtbclk_khz = 600000; in dcn35_update_clocks()
411 else if (!new_clocks->dtbclk_en && new_clocks->ref_dtbclk_khz > 590000) in dcn35_update_clocks()
412 new_clocks->ref_dtbclk_khz = 0; in dcn35_update_clocks()
449 dcn35_update_clocks_update_dtb_dto(clk_mgr, context, new_clocks->ref_dtbclk_khz); in dcn35_update_clocks()
455 clk_mgr_base->clks.ref_dtbclk_khz = new_clocks->ref_dtbclk_khz; in dcn35_update_clocks()
518 should_set_clock(safe_to_lower, new_clocks->ref_dtbclk_khz / 1000, in dcn35_update_clocks()
519 clk_mgr_base->clks.ref_dtbclk_khz / 1000)) { in dcn35_update_clocks()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/
H A Ddcn60_clk_mgr.c243 int ref_dtbclk_khz) in dcn60_update_clocks_update_dtb_dto() argument
245 (void)ref_dtbclk_khz; in dcn60_update_clocks_update_dtb_dto()
319 new_clocks->ref_dtbclk_khz = clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz * 1000; in dcn60_build_update_display_clocks_sequence()
324 …should_set_clock(safe_to_lower, new_clocks->ref_dtbclk_khz / 1000, clk_mgr_base->clks.ref_dtbclk_k… in dcn60_build_update_display_clocks_sequence()
329 (uint16_t)khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz); in dcn60_build_update_display_clocks_sequence()
344 …ock_sequence[num_steps].params.update_hardmin_params.response = &clk_mgr_base->clks.ref_dtbclk_khz; in dcn60_build_update_display_clocks_sequence()
350 …equence[num_steps].params.update_dtbclk_dto_params.ref_dtbclk_khz = &clk_mgr_base->clks.ref_dtbclk… in dcn60_build_update_display_clocks_sequence()
472 dtb_ref_clk_khz = clk_mgr_base->clks.ref_dtbclk_khz; in dcn60_get_dtb_ref_freq_khz()
1002 *params->update_dtbclk_dto_params.ref_dtbclk_khz); in dcn60_execute_block_sequence()
1635 clk_mgr->base.clks.ref_dtbclk_khz != clk_mgr->base.boot_snapshot.dtbclk) { in dcn60_clk_mgr_construct()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_clk_mgr.c300 uint32_t ref_dtbclk = clk_mgr->clks.ref_dtbclk_khz; in dcn31_init_clocks()
304 clk_mgr->clks.ref_dtbclk_khz = ref_dtbclk; // restore ref_dtbclk in dcn31_init_clocks()
665 return clk_mgr_base->clks.ref_dtbclk_khz; in dcn31_get_dtb_ref_freq_khz()
746 clk_mgr->base.base.clks.ref_dtbclk_khz = 600000; in dcn31_clk_mgr_construct()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_clk_mgr.c190 uint32_t ref_dtbclk = clk_mgr->clks.ref_dtbclk_khz; in dcn314_init_clocks()
194 clk_mgr->clks.ref_dtbclk_khz = ref_dtbclk; // restore ref_dtbclk in dcn314_init_clocks()
863 clk_mgr->base.base.clks.ref_dtbclk_khz = 600000; in dcn314_clk_mgr_construct()
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/
H A Ddml2_wrapper_fpu.c421 …out_clks.ref_dtbclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx… in dml2_validate_and_build_resource()
479 …out_clks.ref_dtbclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx… in dml2_validate_and_build_resource()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn60/
H A Ddcn60_hwseq.c363 dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr); in dcn60_setup_audio_dto()
416 dto_params.ref_dtbclk_khz = in dcn60_setup_audio_dto()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn50/
H A Ddcn50_hwseq.c73 clocks->ref_dtbclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000; in dcn50_initialize_min_clocks()