Searched refs:ref_divider (Results 1 – 10 of 10) sorted by relevance
121 * @ref_divider: Reference divider (already known)137 uint32_t ref_divider, in calculate_fb_and_fractional_fb_divider() argument 145 (uint64_t)target_pix_clk_100hz * ref_divider * post_divider; in calculate_fb_and_fractional_fb_divider() 181 * @ref_divider: Reference divider (already known)194 uint32_t ref_divider, in calc_fb_divider_checking_tolerance() 207 ref_divider, in calc_fb_divider_checking_tolerance() 219 ref_divider * post_divider * in calc_fb_divider_checking_tolerance() 234 pll_settings->reference_divider = ref_divider; in calc_fb_divider_checking_tolerance() 256 uint32_t ref_divider; in calc_pll_dividers_in_range() 272 ref_divider in calc_pll_dividers_in_range() 196 calc_fb_divider_checking_tolerance(struct calc_pll_clock_source * calc_pll_cs,struct pll_settings * pll_settings,uint32_t ref_divider,uint32_t post_divider,uint32_t tolerance) calc_fb_divider_checking_tolerance() argument 258 uint32_t ref_divider; calc_pll_dividers_in_range() local [all...]
109 frequency += config->ref_divider >> 1; in tda665x_set_frequency()110 frequency /= config->ref_divider; in tda665x_set_frequency()
19 u32 ref_divider; member
37 .ref_divider = 100000, /* 1/6 MHz */
199 rinfo->panel_info.ref_divider = BIOS_IN16(tmp + 46); in radeon_get_panel_info_BIOS()202 if (rinfo->panel_info.ref_divider != 0 && in radeon_get_panel_info_BIOS()206 pr_debug("ref_divider = %x\n", rinfo->panel_info.ref_divider); in radeon_get_panel_info_BIOS()667 rinfo->panel_info.ref_divider = rinfo->pll.ref_div; in radeon_fixup_panel_info()
64 u16 ref_divider; member
264 int ref_divider; member
1701 newmode->ppll_ref_div = rinfo->panel_info.ref_divider; in radeonfb_set_par()
866 uint32_t ref_divider; in fiji_calculate_sclk_params() local879 ref_divider = 1 + dividers.uc_pll_ref_div; in fiji_calculate_sclk_params()912 (ref_divider * ssInfo.speed_spectrum_rate); in fiji_calculate_sclk_params()
308 uint32_t ref_divider; in ci_calculate_sclk_params() local321 ref_divider = 1 + dividers.uc_pll_ref_div; in ci_calculate_sclk_params()348 (ref_divider * ss_info.speed_spectrum_rate); in ci_calculate_sclk_params()