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Searched refs:ras_block (Results 1 – 25 of 27) sorted by relevance

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/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_nbio.c34 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_nbio_ras_sw_init()
40 strcpy(ras->ras_block.ras_comm.name, "pcie_bif"); in amdgpu_nbio_ras_sw_init()
41 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__PCIE_BIF; in amdgpu_nbio_ras_sw_init()
42 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_nbio_ras_sw_init()
43 adev->nbio.ras_if = &ras->ras_block.ras_comm; in amdgpu_nbio_ras_sw_init()
66 int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) in amdgpu_nbio_ras_late_init() argument
69 r = amdgpu_ras_block_late_init(adev, ras_block); in amdgpu_nbio_ras_late_init()
73 if (amdgpu_ras_is_supported(adev, ras_block->block)) { in amdgpu_nbio_ras_late_init()
84 amdgpu_ras_block_late_fini(adev, ras_block); in amdgpu_nbio_ras_late_init()
H A Damdgpu_mmhub.c33 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_mmhub_ras_sw_init()
39 strcpy(ras->ras_block.ras_comm.name, "mmhub"); in amdgpu_mmhub_ras_sw_init()
40 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__MMHUB; in amdgpu_mmhub_ras_sw_init()
41 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_mmhub_ras_sw_init()
42 adev->mmhub.ras_if = &ras->ras_block.ras_comm; in amdgpu_mmhub_ras_sw_init()
H A Damdgpu_mca.c94 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_mca_mp0_ras_sw_init()
100 strcpy(ras->ras_block.ras_comm.name, "mca.mp0"); in amdgpu_mca_mp0_ras_sw_init()
101 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__MCA; in amdgpu_mca_mp0_ras_sw_init()
102 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_mca_mp0_ras_sw_init()
103 adev->mca.mp0.ras_if = &ras->ras_block.ras_comm; in amdgpu_mca_mp0_ras_sw_init()
118 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_mca_mp1_ras_sw_init()
124 strcpy(ras->ras_block.ras_comm.name, "mca.mp1"); in amdgpu_mca_mp1_ras_sw_init()
125 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__MCA; in amdgpu_mca_mp1_ras_sw_init()
126 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_mca_mp1_ras_sw_init()
127 adev->mca.mp1.ras_if = &ras->ras_block.ras_comm; in amdgpu_mca_mp1_ras_sw_init()
[all …]
H A Damdgpu_sdma.c94 struct ras_common_if *ras_block) in amdgpu_sdma_ras_late_init() argument
98 r = amdgpu_ras_block_late_init(adev, ras_block); in amdgpu_sdma_ras_late_init()
102 if (amdgpu_ras_is_supported(adev, ras_block->block)) { in amdgpu_sdma_ras_late_init()
114 amdgpu_ras_block_late_fini(adev, ras_block); in amdgpu_sdma_ras_late_init()
324 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_sdma_ras_sw_init()
330 strcpy(ras->ras_block.ras_comm.name, "sdma"); in amdgpu_sdma_ras_sw_init()
331 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__SDMA; in amdgpu_sdma_ras_sw_init()
332 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_sdma_ras_sw_init()
333 adev->sdma.ras_if = &ras->ras_block.ras_comm; in amdgpu_sdma_ras_sw_init()
336 if (!ras->ras_block.ras_late_init) in amdgpu_sdma_ras_sw_init()
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H A Dmca_v3_0.c60 .ras_block = {
80 .ras_block = {
100 .ras_block = {
H A Damdgpu_jpeg.c288 int amdgpu_jpeg_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) in amdgpu_jpeg_ras_late_init() argument
292 r = amdgpu_ras_block_late_init(adev, ras_block); in amdgpu_jpeg_ras_late_init()
296 if (amdgpu_ras_is_supported(adev, ras_block->block)) { in amdgpu_jpeg_ras_late_init()
310 amdgpu_ras_block_late_fini(adev, ras_block); in amdgpu_jpeg_ras_late_init()
323 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_jpeg_ras_sw_init()
329 strcpy(ras->ras_block.ras_comm.name, "jpeg"); in amdgpu_jpeg_ras_sw_init()
330 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__JPEG; in amdgpu_jpeg_ras_sw_init()
331 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON; in amdgpu_jpeg_ras_sw_init()
332 adev->jpeg.ras_if = &ras->ras_block.ras_comm; in amdgpu_jpeg_ras_sw_init()
334 if (!ras->ras_block.ras_late_init) in amdgpu_jpeg_ras_sw_init()
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H A Damdgpu_gfx.c978 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) in amdgpu_gfx_ras_late_init() argument
982 if (amdgpu_ras_is_supported(adev, ras_block->block)) { in amdgpu_gfx_ras_late_init()
989 r = amdgpu_ras_block_late_init(adev, ras_block); in amdgpu_gfx_ras_late_init()
1002 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0); in amdgpu_gfx_ras_late_init()
1007 amdgpu_ras_block_late_fini(adev, ras_block); in amdgpu_gfx_ras_late_init()
1024 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_gfx_ras_sw_init()
1030 strcpy(ras->ras_block.ras_comm.name, "gfx"); in amdgpu_gfx_ras_sw_init()
1031 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__GFX; in amdgpu_gfx_ras_sw_init()
1032 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_gfx_ras_sw_init()
1033 adev->gfx.ras_if = &ras->ras_block.ras_comm; in amdgpu_gfx_ras_sw_init()
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H A Damdgpu_vcn.c1293 int amdgpu_vcn_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) in amdgpu_vcn_ras_late_init() argument
1297 r = amdgpu_ras_block_late_init(adev, ras_block); in amdgpu_vcn_ras_late_init()
1301 if (amdgpu_ras_is_supported(adev, ras_block->block)) { in amdgpu_vcn_ras_late_init()
1315 amdgpu_ras_block_late_fini(adev, ras_block); in amdgpu_vcn_ras_late_init()
1328 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_vcn_ras_sw_init()
1334 strcpy(ras->ras_block.ras_comm.name, "vcn"); in amdgpu_vcn_ras_sw_init()
1335 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__VCN; in amdgpu_vcn_ras_sw_init()
1336 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON; in amdgpu_vcn_ras_sw_init()
1337 adev->vcn.ras_if = &ras->ras_block.ras_comm; in amdgpu_vcn_ras_sw_init()
1339 if (!ras->ras_block.ras_late_init) in amdgpu_vcn_ras_sw_init()
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H A Djpeg_v5_0_1.c1073 static int jpeg_v5_0_1_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) in jpeg_v5_0_1_ras_late_init() argument
1077 r = amdgpu_ras_block_late_init(adev, ras_block); in jpeg_v5_0_1_ras_late_init()
1086 if (amdgpu_ras_is_supported(adev, ras_block->block) && in jpeg_v5_0_1_ras_late_init()
1096 amdgpu_ras_block_late_fini(adev, ras_block); in jpeg_v5_0_1_ras_late_init()
1102 .ras_block = {
H A Dumc_v8_14.c156 .ras_block = {
H A Dhdp_v4_0.c166 .ras_block = {
H A Djpeg_v4_0_3.c1494 static int jpeg_v4_0_3_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) in jpeg_v4_0_3_ras_late_init() argument
1498 r = amdgpu_ras_block_late_init(adev, ras_block); in jpeg_v4_0_3_ras_late_init()
1502 if (amdgpu_ras_is_supported(adev, ras_block->block) && in jpeg_v4_0_3_ras_late_init()
1517 amdgpu_ras_block_late_fini(adev, ras_block); in jpeg_v4_0_3_ras_late_init()
1523 .ras_block = {
H A Damdgpu_mca.h72 struct amdgpu_ras_block_object ras_block; member
H A Dsdma_v4_4.c271 .ras_block = {
H A Dvcn_v5_0_1.c1781 static int vcn_v5_0_1_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) in vcn_v5_0_1_ras_late_init() argument
1785 r = amdgpu_ras_block_late_init(adev, ras_block); in vcn_v5_0_1_ras_late_init()
1794 if (amdgpu_ras_is_supported(adev, ras_block->block) && in vcn_v5_0_1_ras_late_init()
1804 amdgpu_ras_block_late_fini(adev, ras_block); in vcn_v5_0_1_ras_late_init()
1810 .ras_block = {
H A Dvcn_v4_0_3.c2214 static int vcn_v4_0_3_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) in vcn_v4_0_3_ras_late_init() argument
2218 r = amdgpu_ras_block_late_init(adev, ras_block); in vcn_v4_0_3_ras_late_init()
2222 if (amdgpu_ras_is_supported(adev, ras_block->block) && in vcn_v4_0_3_ras_late_init()
2237 amdgpu_ras_block_late_fini(adev, ras_block); in vcn_v4_0_3_ras_late_init()
2243 .ras_block = {
H A Dumc_v8_7.c440 .ras_block = {
H A Dumc_v8_10.c451 .ras_block = {
H A Dumc_v6_7.c522 .ras_block = {
H A Djpeg_v2_5.c856 .ras_block = {
H A Djpeg_v4_0.c864 .ras_block = {
H A Dmmhub_v1_0.c835 .ras_block = {
H A Dsdma_v6_0.c1255 .ras_block = {
H A Dvcn_v4_0.c2320 .ras_block = {
H A Dsdma_v4_0.c2713 .ras_block = {

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