Searched refs:quad_part (Results 1 – 11 of 11) sorted by relevance
93 if (hwseq->fb_base.quad_part <= addr->quad_part && in gpu_addr_to_uma()94 addr->quad_part < hwseq->fb_top.quad_part) { in gpu_addr_to_uma()95 addr->quad_part -= hwseq->fb_base.quad_part; in gpu_addr_to_uma()96 addr->quad_part += hwseq->fb_offset.quad_part; in gpu_addr_to_uma()98 } else if (hwseq->fb_offset.quad_part <= addr->quad_part && in gpu_addr_to_uma()99 addr->quad_part <= hwseq->uma_top.quad_part) { in gpu_addr_to_uma()101 } else if (addr->quad_part == 0) { in gpu_addr_to_uma()216 hws->fb_base.quad_part <<= 24; in read_mmhub_vm_setup()219 hws->fb_top.quad_part <<= 24; in read_mmhub_vm_setup()221 hws->fb_offset.quad_part <<= 24; in read_mmhub_vm_setup()[all …]
80 union large_integer start_address_shift = {.quad_part = params->start_address.quad_part >> 5}; in mmhubbub32_warmup_mcif()
535 if (!table || smu_dpm_clks->mc_address.quad_part == 0) in dcn42_get_dpm_table_from_smu()707 &clk_mgr_dcn42->smu_wm_set.mc_address.quad_part); in dcn42_notify_wm_ranges()713 if (!table || clk_mgr_dcn42->smu_wm_set.mc_address.quad_part == 0) in dcn42_notify_wm_ranges()737 if (clk_mgr_dcn42->smu_wm_set.wm_set && clk_mgr_dcn42->smu_wm_set.mc_address.quad_part != 0) in dcn42_notify_wm_ranges()902 &smu_dpm_clks.mc_address.quad_part); in dcn42_get_smu_clocks()905 if (clk_mgr_base->ctx->dc->debug.pstate_enabled && smu_dpm_clks.mc_address.quad_part != 0) { in dcn42_get_smu_clocks()1006 if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0) in dcn42_get_smu_clocks()1102 if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0) in dcn42_clk_mgr_destroy()
80 union large_integer start_address_shift = {.quad_part = params->start_address.quad_part >> 5}; in mmhubbub3_warmup_mcif()
45 uint64_t quad_part; member
335 if (attributes->address.quad_part == 0) { in dc_stream_check_cursor_attributes()872 pipe_ctx->stream->dmdata_address.quad_part != 0) { in dc_stream_set_dynamic_metadata()
3799 …>num_steps].params.hubp_set_vm_system_aperture_settings_params.sys_default.quad_part = sys_default; in hwss_add_hubp_set_vm_system_aperture_settings()3800 …q_state->num_steps].params.hubp_set_vm_system_aperture_settings_params.sys_low.quad_part = sys_low; in hwss_add_hubp_set_vm_system_aperture_settings()3801 …state->num_steps].params.hubp_set_vm_system_aperture_settings_params.sys_high.quad_part = sys_high; in hwss_add_hubp_set_vm_system_aperture_settings()
3783 pipe_ctx->stream->dmdata_address.quad_part != 0) in commit_planes_do_stream_update()
1535 pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12; in mmhub_read_system_context()1536 pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12; in mmhub_read_system_context()1537 pa_config->gart_config.page_table_base_addr = page_table_base.quad_part; in mmhub_read_system_context()10768 wb_info->mcif_warmup_params.start_address.quad_part = afb->address; in dm_set_writeback()
2370 compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr; in enable_fbc()
3623 pipe_ctx->stream->cursor_attributes.address.quad_part != 0) { in dcn401_update_dchubp_dpp_sequence()