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Searched refs:post_divider (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/radeon/
H A Drv730_dpm.c50 u32 reference_divider, post_divider; in rv730_populate_sclk_value() local
62 post_divider = ((dividers.post_div >> 4) & 0xf) + in rv730_populate_sclk_value()
65 post_divider = 1; in rv730_populate_sclk_value()
67 tmp = (u64) engine_clock * reference_divider * post_divider * 16384; in rv730_populate_sclk_value()
90 u32 vco_freq = engine_clock * post_divider; in rv730_populate_sclk_value()
129 u32 post_divider, reference_divider; in rv730_populate_mclk_value() local
140 post_divider = ((dividers.post_div >> 4) & 0xf) + in rv730_populate_mclk_value()
143 post_divider = 1; in rv730_populate_mclk_value()
165 u32 vco_freq = memory_clock * post_divider; in rv730_populate_mclk_value()
H A Drv6xx_dpm.c150 step->post_divider = 2 + (dividers.post_div & 0xF) + (dividers.post_div >> 4); in rv6xx_convert_clock_to_stepping()
152 step->post_divider = 1; in rv6xx_convert_clock_to_stepping()
154 step->vco_frequency = clock * step->post_divider; in rv6xx_convert_clock_to_stepping()
173 if (step->post_divider == 1) in rv6xx_output_stepping()
176 u32 lo_len = (step->post_divider - 2) / 2; in rv6xx_output_stepping()
177 u32 hi_len = step->post_divider - 2 - lo_len; in rv6xx_output_stepping()
199 next.post_divider = cur->post_divider; in rv6xx_next_vco_step()
213 return (cur->post_divider > target->post_divider) && in rv6xx_can_step_post_div()
214 ((cur->vco_frequency * target->post_divider) <= in rv6xx_can_step_post_div()
215 (target->vco_frequency * (cur->post_divider - 1))); in rv6xx_can_step_post_div()
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H A Drv6xx_dpm.h33 u32 post_divider; member
H A Drv770_dpm.c326 u32 post_divider, reference_divider, feedback_divider8; in rv770_calculate_fractional_mpll_feedback_divider() local
334 post_divider = dividers->post_div; in rv770_calculate_fractional_mpll_feedback_divider()
338 (8 * fyclk * reference_divider * post_divider) / reference_clock; in rv770_calculate_fractional_mpll_feedback_divider()
503 u32 reference_divider, post_divider; in rv770_populate_sclk_value() local
515 post_divider = (0x0f & (dividers.post_div >> 4)) + (0x0f & dividers.post_div) + 2; in rv770_populate_sclk_value()
517 post_divider = 1; in rv770_populate_sclk_value()
519 tmp = (u64) engine_clock * reference_divider * post_divider * 16384; in rv770_populate_sclk_value()
541 u32 vco_freq = engine_clock * post_divider; in rv770_populate_sclk_value()
H A Dci_dpm.c2630 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider; in ci_populate_smc_uvd_level()
2638 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider; in ci_populate_smc_uvd_level()
2671 table->VceLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_vce_level()
2704 table->AcpLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_acp_level()
2736 table->SamuLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_samu_level()
2975 table->ACPILevel.SclkDid = (u8)dividers.post_divider; in ci_populate_smc_acpi_level()
3167 sclk->SclkDid = (u8)dividers.post_divider; in ci_calculate_sclk_params()
H A Dradeon_atombios.c2917 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv; in radeon_atom_get_clock_dividers()
2934 dividers->post_divider = args.v6_out.ulClock.ucPostDiv; in radeon_atom_get_clock_dividers()
/linux/drivers/video/fbdev/aty/
H A Dmach64_gx.c346 u32 post_divider; in aty_var_to_pll_18818() local
352 post_divider = 1; in aty_var_to_pll_18818()
361 post_divider *= 2; in aty_var_to_pll_18818()
372 switch (post_divider) { in aty_var_to_pll_18818()
392 pll->ics2595.post_divider = post_divider; in aty_var_to_pll_18818()
558 pll->ics2595.post_divider = divider; /* fuer nix */ in aty_var_to_pll_1703()
676 pll->ics2595.post_divider = 0; in aty_var_to_pll_8398()
794 pll->ics2595.post_divider = divider; /* fuer nix */ in aty_var_to_pll_408()
H A Dradeon_monitor.c200 rinfo->panel_info.post_divider = BIOS_IN8(tmp + 48); in radeon_get_panel_info_BIOS()
207 pr_debug("post_divider = %x\n", rinfo->panel_info.post_divider); in radeon_get_panel_info_BIOS()
669 rinfo->panel_info.post_divider = (ppll_divn >> 16) & 0x7; in radeon_fixup_panel_info()
675 (rinfo->panel_info.post_divider << 16), in radeon_fixup_panel_info()
H A Datyfb.h81 u32 post_divider; member
H A Dradeonfb.h265 int post_divider; member
H A Dradeon_base.c1700 (rinfo->panel_info.post_divider << 16); in radeonfb_set_par()
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_clock_source.c138 uint32_t post_divider, in calculate_fb_and_fractional_fb_divider() argument
145 (uint64_t)target_pix_clk_100hz * ref_divider * post_divider; in calculate_fb_and_fractional_fb_divider()
197 uint32_t post_divider, in calc_fb_divider_checking_tolerance() argument
210 post_divider, in calc_fb_divider_checking_tolerance()
221 ref_divider * post_divider * in calc_fb_divider_checking_tolerance()
239 pll_settings->pix_clk_post_divider = post_divider; in calc_fb_divider_checking_tolerance()
243 div_u64((u64)actual_calculated_clock_100hz * post_divider, 10); in calc_fb_divider_checking_tolerance()
259 uint32_t post_divider; in calc_pll_dividers_in_range() local
270 post_divider = max_post_divider; in calc_pll_dividers_in_range()
271 post_divider >= min_post_divider; in calc_pll_dividers_in_range()
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