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Searched refs:pll_prediv (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/media/usb/dvb-usb/
H A Ddib0700_devices.c224 .pll_prediv = 1,
390 .pll_prediv = 1,
659 .pll_prediv = 1,
951 .pll_prediv = 1,
1177 .pll_prediv = 1,
1516 .pll_prediv = 1,
1607 .io.pll_prediv = 1,
1953 .pll_prediv = 1,
2000 .io.pll_prediv = 3,
2030 u32 pll_prediv; member
[all …]
H A Ddib0700_core.c401 u8 pll_src, u8 pll_range, u8 clock_gpio3, u16 pll_prediv, in dib0700_set_clock() argument
415 st->buf[2] = (pll_prediv >> 8) & 0xff; /* MSB */ in dib0700_set_clock()
416 st->buf[3] = pll_prediv & 0xff; /* LSB */ in dib0700_set_clock()
/linux/drivers/media/dvb-frontends/
H A Ddib0090.h20 u8 pll_prediv:6; member
H A Ddibx000_common.h119 u8 pll_prediv; member
H A Ddib7000p.c448 …e, 1856, (!bw->pll_reset << 13) | (bw->pll_range << 12) | (bw->pll_ratio << 6) | (bw->pll_prediv)); in dib7000p_reset_pll()
462 …dib7000p_write_word(state, 903, (bw->pll_prediv << 5) | (((bw->pll_ratio >> 6) & 0x3) << 3) | (bw-… in dib7000p_reset_pll()
495 if (loopdiv && bw && (bw->pll_prediv != prediv || bw->pll_ratio != loopdiv)) { in dib7000p_update_pll()
496 …div: old = %d new = %d ; loopdiv : old = %d new = %d)\n", prediv, bw->pll_prediv, loopdiv, bw->pl… in dib7000p_update_pll()
501 …dib7000p_write_word(state, 1856, reg_1856 | ((bw->pll_ratio & 0x3f) << 6) | (bw->pll_prediv & 0x3f… in dib7000p_update_pll()
506 internal = 1000 * (xtal / bw->pll_prediv) * bw->pll_ratio; /* new internal */ in dib7000p_update_pll()
H A Ddib0090.c533 … != ((cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv)) && (!cfg->in_s… in dib0090_reset_digital()
545 …<< 15) | (0 << 13) | (cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv); in dib0090_reset_digital()
605 … != ((cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv)) && !cfg->io.pl… in dib0090_fw_reset_digital()
616 …<< 15) | (0 << 13) | (cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv); in dib0090_fw_reset_digital()
H A Ddib7000m.c415 reg_910 |= (bw->pll_prediv << 5); in dib7000m_reset_pll()
431 dib7000m_write_word(state, 907, (bw->pll_prediv << 8) | (bw->pll_ratio << 0)); in dib7000mc_reset_pll()