Home
last modified time | relevance | path

Searched refs:pll_mux (Results 1 – 3 of 3) sorted by relevance

/linux/drivers/clk/rockchip/
H A Dclk-pll.c30 struct clk_mux pll_mux; member
199 struct clk_mux *pll_mux = &pll->pll_mux; in rockchip_rk3036_pll_set_params() local
214 cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); in rockchip_rk3036_pll_set_params()
216 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); in rockchip_rk3036_pll_set_params()
251 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3036_pll_set_params()
436 struct clk_mux *pll_mux = &pll->pll_mux; in rockchip_rk3066_pll_set_params() local
448 cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); in rockchip_rk3066_pll_set_params()
450 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); in rockchip_rk3066_pll_set_params()
486 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3066_pll_set_params()
683 struct clk_mux *pll_mux = &pll->pll_mux; in rockchip_rk3399_pll_set_params() local
[all …]
/linux/drivers/clk/socfpga/
H A Dclk-s10.c14 static const struct clk_parent_data pll_mux[] = { variable
185 { STRATIX10_MAIN_PLL_CLK, "main_pll", pll_mux, ARRAY_SIZE(pll_mux),
187 { STRATIX10_PERIPH_PLL_CLK, "periph_pll", pll_mux, ARRAY_SIZE(pll_mux),
H A Dclk-agilex.c14 static const struct clk_parent_data pll_mux[] = { variable
229 { AGILEX_MAIN_PLL_CLK, "main_pll", pll_mux, ARRAY_SIZE(pll_mux),
231 { AGILEX_PERIPH_PLL_CLK, "periph_pll", pll_mux, ARRAY_SIZE(pll_mux),