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Searched refs:plane_id (Results 1 – 25 of 32) sorted by relevance

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/linux/drivers/gpu/drm/i915/display/
H A Dintel_sprite_regs.h230 #define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \ argument
231 _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
232 #define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \ argument
233 _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b)))
237 #define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR) argument
266 #define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF) argument
270 #define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE) argument
274 #define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS) argument
282 #define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE) argument
290 #define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL) argument
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H A Dskl_universal_plane.c247 enum plane_id plane_id) in icl_is_nv12_y_plane() argument
250 icl_nv12_y_plane_mask(dev_priv) & BIT(plane_id); in icl_is_nv12_y_plane()
258 bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id) in icl_is_hdr_plane() argument
261 icl_hdr_plane_mask() & BIT(plane_id); in icl_is_hdr_plane()
610 enum plane_id plane_id = plane->id; in icl_program_input_csc() local
652 intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 0), in icl_program_input_csc()
654 intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 1), in icl_program_input_csc()
656 intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 2), in icl_program_input_csc()
658 intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 3), in icl_program_input_csc()
660 intel_de_write_dsb(display, dsb, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 4), in icl_program_input_csc()
[all …]
H A Dskl_universal_plane.h19 enum plane_id;
23 enum pipe pipe, enum plane_id plane_id);
36 enum plane_id plane_id);
38 bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id);
H A Dskl_watermark.c358 enum plane_id plane_id; in skl_crtc_can_enable_sagv() local
370 for_each_plane_id_on_crtc(crtc, plane_id) { in skl_crtc_can_enable_sagv()
372 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_crtc_can_enable_sagv()
392 for_each_plane_id_on_crtc(crtc, plane_id) { in skl_crtc_can_enable_sagv()
394 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_crtc_can_enable_sagv()
410 enum plane_id plane_id; in tgl_crtc_can_enable_sagv() local
415 for_each_plane_id_on_crtc(crtc, plane_id) { in tgl_crtc_can_enable_sagv()
417 &crtc_state->wm.skl.optimal.planes[plane_id]; in tgl_crtc_can_enable_sagv()
802 const enum plane_id plane_id, in skl_ddb_get_hw_plane_state() argument
811 if (plane_id == PLANE_CURSOR) { in skl_ddb_get_hw_plane_state()
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H A Dintel_dpt_common.c19 enum plane_id plane_id; in intel_dpt_configure() local
21 for_each_plane_id_on_crtc(crtc, plane_id) { in intel_dpt_configure()
22 if (plane_id == PLANE_CURSOR) in intel_dpt_configure()
25 intel_de_rmw(i915, PLANE_CHICKEN(pipe, plane_id), in intel_dpt_configure()
H A Dintel_sprite.c72 enum plane_id plane_id = plane->id; in chv_sprite_update_csc() local
103 intel_de_write_fw(display, SPCSCYGOFF(plane_id), in chv_sprite_update_csc()
105 intel_de_write_fw(display, SPCSCCBOFF(plane_id), in chv_sprite_update_csc()
107 intel_de_write_fw(display, SPCSCCROFF(plane_id), in chv_sprite_update_csc()
110 intel_de_write_fw(display, SPCSCC01(plane_id), in chv_sprite_update_csc()
112 intel_de_write_fw(display, SPCSCC23(plane_id), in chv_sprite_update_csc()
114 intel_de_write_fw(display, SPCSCC45(plane_id), in chv_sprite_update_csc()
116 intel_de_write_fw(display, SPCSCC67(plane_id), in chv_sprite_update_csc()
118 intel_de_write_fw(display, SPCSCC8(plane_id), SPCSC_C0(csc[8])); in chv_sprite_update_csc()
120 intel_de_write_fw(display, SPCSCYGICLAMP(plane_id), in chv_sprite_update_csc()
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H A Di9xx_wm.c919 static int g4x_plane_fifo_size(enum plane_id plane_id, int level) in g4x_plane_fifo_size() argument
935 switch (plane_id) { in g4x_plane_fifo_size()
943 MISSING_CASE(plane_id); in g4x_plane_fifo_size()
1018 int level, enum plane_id plane_id, u16 value) in g4x_raw_plane_wm_set() argument
1026 dirty |= raw->plane[plane_id] != value; in g4x_raw_plane_wm_set()
1027 raw->plane[plane_id] = value; in g4x_raw_plane_wm_set()
1061 enum plane_id plane_id = plane->id; in g4x_raw_plane_wm_compute() local
1066 dirty |= g4x_raw_plane_wm_set(crtc_state, 0, plane_id, 0); in g4x_raw_plane_wm_compute()
1067 if (plane_id == PLANE_PRIMARY) in g4x_raw_plane_wm_compute()
1077 max_wm = g4x_plane_fifo_size(plane_id, level); in g4x_raw_plane_wm_compute()
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H A Dskl_watermark.h53 enum plane_id plane_id,
56 enum plane_id plane_id);
H A Dintel_bw.c778 enum plane_id plane_id; in intel_bw_crtc_data_rate() local
780 for_each_plane_id_on_crtc(crtc, plane_id) { in intel_bw_crtc_data_rate()
785 if (plane_id == PLANE_CURSOR) in intel_bw_crtc_data_rate()
788 data_rate += crtc_state->data_rate[plane_id]; in intel_bw_crtc_data_rate()
791 data_rate += crtc_state->data_rate_y[plane_id]; in intel_bw_crtc_data_rate()
1168 enum plane_id plane_id, in skl_plane_calc_dbuf_bw() argument
1183 crtc_bw->active_planes[slice] |= BIT(plane_id); in skl_plane_calc_dbuf_bw()
1193 enum plane_id plane_id; in skl_crtc_calc_dbuf_bw() local
1200 for_each_plane_id_on_crtc(crtc, plane_id) { in skl_crtc_calc_dbuf_bw()
1205 if (plane_id == PLANE_CURSOR) in skl_crtc_calc_dbuf_bw()
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H A Dintel_atomic_plane.c667 intel_crtc_get_plane(struct intel_crtc *crtc, enum plane_id plane_id) in intel_crtc_get_plane() argument
673 if (plane->id == plane_id) in intel_crtc_get_plane()
738 enum plane_id plane_id = plane->id; in skl_next_plane_to_commit() local
741 !(*update_mask & BIT(plane_id))) in skl_next_plane_to_commit()
744 if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb[plane_id], in skl_next_plane_to_commit()
745 ddb, I915_MAX_PLANES, plane_id) || in skl_next_plane_to_commit()
746 skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_y[plane_id], in skl_next_plane_to_commit()
747 ddb_y, I915_MAX_PLANES, plane_id)) in skl_next_plane_to_commit()
750 *update_mask &= ~BIT(plane_id); in skl_next_plane_to_commit()
751 ddb[plane_id] = crtc_state->wm.skl.plane_ddb[plane_id]; in skl_next_plane_to_commit()
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H A Dintel_fbc_regs.h66 #define DPFC_CTL_PLANE_BINDING(plane_id) REG_FIELD_PREP(DPFC_CTL_PLANE_BINDING_MASK, (plane_id)) argument
H A Dintel_cursor.c623 enum plane_id plane_id = plane->id; in skl_write_cursor_wm() local
627 &crtc_state->wm.skl.plane_ddb[plane_id]; in skl_write_cursor_wm()
632 skl_cursor_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level))); in skl_write_cursor_wm()
635 skl_cursor_wm_reg_val(skl_plane_trans_wm(pipe_wm, plane_id))); in skl_write_cursor_wm()
638 const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id]; in skl_write_cursor_wm()
H A Dintel_display_debugfs.c710 enum plane_id plane_id; in i915_ddb_info() local
714 for_each_plane_id_on_crtc(crtc, plane_id) { in i915_ddb_info()
715 entry = &crtc_state->wm.skl.plane_ddb[plane_id]; in i915_ddb_info()
716 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane_id + 1, in i915_ddb_info()
/linux/drivers/gpu/drm/kmb/
H A Dkmb_plane.c72 int plane_id = kmb_plane->id; in check_pixel_format() local
76 init_disp_cfg = kmb->init_disp_cfg[plane_id]; in check_pixel_format()
98 int plane_id = kmb_plane->id; in kmb_plane_atomic_check() local
106 init_disp_cfg = kmb->init_disp_cfg[plane_id]; in kmb_plane_atomic_check()
145 int plane_id = kmb_plane->id; in kmb_plane_atomic_disable() local
150 if (WARN_ON(plane_id >= KMB_MAX_PLANES)) in kmb_plane_atomic_disable()
153 switch (plane_id) { in kmb_plane_atomic_disable()
155 kmb->plane_status[plane_id].ctrl = LCD_CTRL_VL1_ENABLE; in kmb_plane_atomic_disable()
158 kmb->plane_status[plane_id].ctrl = LCD_CTRL_VL2_ENABLE; in kmb_plane_atomic_disable()
162 kmb->plane_status[plane_id].disable = true; in kmb_plane_atomic_disable()
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H A Dkmb_drv.c207 int plane_id, dma0_state, dma1_state; in handle_lcd_irq() local
223 for (plane_id = LAYER_0; in handle_lcd_irq()
224 plane_id < KMB_MAX_PLANES; plane_id++) { in handle_lcd_irq()
225 if (kmb->plane_status[plane_id].disable) { in handle_lcd_irq()
228 (plane_id), in handle_lcd_irq()
232 kmb->plane_status[plane_id].ctrl); in handle_lcd_irq()
247 kmb->plane_status[plane_id].disable = false; in handle_lcd_irq()
/linux/drivers/gpu/drm/sti/
H A Dsti_mixer.c239 int plane_id, depth = plane->drm_plane.state->normalized_zpos; in sti_mixer_set_plane_depth() local
245 plane_id = GAM_DEPTH_GDP0_ID; in sti_mixer_set_plane_depth()
248 plane_id = GAM_DEPTH_GDP1_ID; in sti_mixer_set_plane_depth()
251 plane_id = GAM_DEPTH_GDP2_ID; in sti_mixer_set_plane_depth()
254 plane_id = GAM_DEPTH_GDP3_ID; in sti_mixer_set_plane_depth()
257 plane_id = GAM_DEPTH_VID0_ID; in sti_mixer_set_plane_depth()
271 if ((val & mask) == plane_id << (3 * i)) in sti_mixer_set_plane_depth()
276 plane_id = plane_id << (3 * depth); in sti_mixer_set_plane_depth()
281 plane_id, mask); in sti_mixer_set_plane_depth()
284 val |= plane_id; in sti_mixer_set_plane_depth()
/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/
H A Ddml21_utils.h19 int dml21_find_dml_pipe_idx_by_plane_id(struct dml2_context *ctx, unsigned int plane_id);
20 …plane_id(const struct dc_state *state, const struct dc_plane_state *plane, unsigned int *plane_id);
45 unsigned int dml21_get_dc_plane_idx_from_plane_id(unsigned int plane_id);
H A Ddml21_utils.c25 int dml21_find_dml_pipe_idx_by_plane_id(struct dml2_context *ctx, unsigned int plane_id) in dml21_find_dml_pipe_idx_by_plane_id() argument
29 …dx_to_plane_id_valid[i] && ctx->v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id[i] == plane_id) in dml21_find_dml_pipe_idx_by_plane_id()
36 …_plane_id(const struct dc_state *state, const struct dc_plane_state *plane, unsigned int *plane_id) in dml21_get_plane_id() argument
40 if (!plane_id) in dml21_get_plane_id()
46 *plane_id = (i << 16) | j; in dml21_get_plane_id()
55 unsigned int dml21_get_dc_plane_idx_from_plane_id(unsigned int plane_id) in dml21_get_dc_plane_idx_from_plane_id() argument
57 return 0xffff & plane_id; in dml21_get_dc_plane_idx_from_plane_id()
H A Ddml21_translation_helper.c913 …lane_id(const struct dc_state *context, const struct dc_plane_state *plane, unsigned int *plane_id) in dml21_wrapper_get_plane_id() argument
917 if (!plane_id) in dml21_wrapper_get_plane_id()
923 *plane_id = (i << 16) | j; in dml21_wrapper_get_plane_id()
950 unsigned int plane_id; in map_plane_to_dml21_display_cfg() local
954 if (!dml21_wrapper_get_plane_id(context, plane, &plane_id)) { in map_plane_to_dml21_display_cfg()
960 …_to_plane_id_valid[i] && dml_ctx->v21.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id[i] == plane_id) { in map_plane_to_dml21_display_cfg()
/linux/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddml2_utils.c205 static int find_dml_pipe_idx_by_plane_id(struct dml2_context *ctx, unsigned int plane_id) in find_dml_pipe_idx_by_plane_id() argument
209 …ane_id_valid[i] && ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id[i] == plane_id) in find_dml_pipe_idx_by_plane_id()
217 unsigned int stream_id, unsigned int plane_index, unsigned int *plane_id) in get_plane_id() argument
222 if (!plane_id) in get_plane_id()
230 *plane_id = (i << 16) | j; in get_plane_id()
281 unsigned int dc_pipe_ctx_index, dml_pipe_idx, plane_id; in dml2_calculate_rq_and_dlg_params() local
307 …g.dml_pipe_idx_to_plane_index[context->res_ctx.pipe_ctx[dc_pipe_ctx_index].pipe_idx], &plane_id)) { in dml2_calculate_rq_and_dlg_params()
308 dml_pipe_idx = find_dml_pipe_idx_by_plane_id(in_ctx, plane_id); in dml2_calculate_rq_and_dlg_params()
513 unsigned int i = 0, dml_pipe_idx = 0, plane_id = 0; in dml2_verify_det_buffer_configuration() local
524 …_pipe_mapping.dml_pipe_idx_to_plane_index[display_state->res_ctx.pipe_ctx[i].pipe_idx], &plane_id)) in dml2_verify_det_buffer_configuration()
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/linux/drivers/gpu/drm/i915/gvt/
H A Ddmabuf.c257 int plane_id) in vgpu_get_plane_info() argument
265 if (plane_id == DRM_PLANE_TYPE_PRIMARY) { in vgpu_get_plane_info()
295 } else if (plane_id == DRM_PLANE_TYPE_CURSOR) { in vgpu_get_plane_info()
317 gvt_vgpu_err("invalid plane id:%d\n", plane_id); in vgpu_get_plane_info()
/linux/drivers/media/platform/nvidia/tegra-vde/
H A Dh264.c674 unsigned int plane_id, in tegra_vde_validate_vb_size() argument
677 u64 offset = vb->planes[plane_id].data_offset; in tegra_vde_validate_vb_size()
680 if (offset + min_size > vb2_plane_size(vb, plane_id)) { in tegra_vde_validate_vb_size()
682 plane_id, vb2_plane_size(vb, plane_id), offset, min_size); in tegra_vde_validate_vb_size()
/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_trace.h651 TP_PROTO(uint32_t crtc_id, uint32_t plane_id,
655 TP_ARGS(crtc_id, plane_id, state, pstate, stage_idx,
659 __field( uint32_t, plane_id )
673 __entry->plane_id = plane_id;
689 __entry->crtc_id, __entry->plane_id, __entry->fb_id,
/linux/include/uapi/drm/
H A Ddrm_mode.h297 __u32 plane_id; member
334 __u32 plane_id; member
/linux/drivers/gpu/drm/
H A Ddrm_plane.c836 plane = drm_plane_find(dev, file_priv, plane_resp->plane_id); in drm_mode_getplane()
856 plane_resp->plane_id = plane->base.id; in drm_mode_getplane()
1124 plane = drm_plane_find(dev, file_priv, plane_req->plane_id); in drm_mode_setplane()
1127 plane_req->plane_id); in drm_mode_setplane()

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