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Searched refs:pl1 (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/xe/
H A Dxe_gt_throttle.c61 u32 pl1 = xe_gt_throttle_get_limit_reasons(gt) & POWER_LIMIT_1_MASK; in read_reason_pl1() local
63 return pl1; in read_reason_pl1()
131 bool pl1 = !!read_reason_pl1(gt); in reason_pl1_show() local
133 return sysfs_emit(buff, "%u\n", pl1); in reason_pl1_show()
/linux/drivers/pinctrl/tegra/
H A Dpinctrl-tegra210.c1509 …PINGROUP(pl1, SOC, RSVD1, RSVD2, RSVD3, 0x3278, Y, Y, N, N,…
1532 DRV_PINGROUP(pl1, 0x9f8, 0x0, -1, -1, -1, -1, 28, 2, 30, 2),
/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra210-p2595.dtsi604 pl1 {
605 nvidia,pins = "pl1";
H A Dtegra210-p2571.dts615 pl1 {
616 nvidia,pins = "pl1";
H A Dtegra210-p2597.dtsi631 pl1 {
632 nvidia,pins = "pl1";
H A Dtegra210-smaug.dts666 pl1 {
667 nvidia,pins = "pl1";
H A Dtegra210-p2894.dtsi631 pl1 {
632 nvidia,pins = "pl1";
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dsmu7_hwmgr.c4706 static inline bool smu7_are_power_levels_equal(const struct smu7_performance_level *pl1, in smu7_are_power_levels_equal() argument
4709 return ((pl1->memory_clock == pl2->memory_clock) && in smu7_are_power_levels_equal()
4710 (pl1->engine_clock == pl2->engine_clock) && in smu7_are_power_levels_equal()
4711 (pl1->pcie_gen == pl2->pcie_gen) && in smu7_are_power_levels_equal()
4712 (pl1->pcie_lane == pl2->pcie_lane)); in smu7_are_power_levels_equal()
H A Dvega10_hwmgr.c5022 const struct vega10_performance_level *pl1, in vega10_are_power_levels_equal() argument
5025 return ((pl1->soc_clock == pl2->soc_clock) && in vega10_are_power_levels_equal()
5026 (pl1->gfx_clock == pl2->gfx_clock) && in vega10_are_power_levels_equal()
5027 (pl1->mem_clock == pl2->mem_clock)); in vega10_are_power_levels_equal()