| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| H A D | dcn20_hwseq.h | 34 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
36 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
43 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);
44 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);
45 bool dcn20_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
47 bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
50 struct pipe_ctx *pipe_ctx,
54 void dcn20_enable_stream(struct pipe_ctx *pipe_ctx);
55 void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,
57 void dcn20_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);
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| H A D | dcn20_hwseq.c | 220 struct pipe_ctx *pipe_ctx, in dcn20_setup_gsl_group_as_lock() argument
232 if (pipe_ctx->stream_res.gsl_group > 0) in dcn20_setup_gsl_group_as_lock()
237 pipe_ctx->stream_res.gsl_group = group_idx; in dcn20_setup_gsl_group_as_lock()
259 group_idx = pipe_ctx->stream_res.gsl_group; in dcn20_setup_gsl_group_as_lock()
263 pipe_ctx->stream_res.gsl_group = 0; in dcn20_setup_gsl_group_as_lock()
287 if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL) { in dcn20_setup_gsl_group_as_lock()
288 pipe_ctx->stream_res.tg->funcs->set_gsl( in dcn20_setup_gsl_group_as_lock()
289 pipe_ctx->stream_res.tg, in dcn20_setup_gsl_group_as_lock()
291 if (pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) in dcn20_setup_gsl_group_as_lock()
292 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select( in dcn20_setup_gsl_group_as_lock()
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| /linux/drivers/gpu/drm/amd/display/dc/link/ |
| H A D | link_dpms.c | 152 struct pipe_ctx *pipes[MAX_PIPES]; in link_set_all_streams_dpms_off_for_link()
197 const struct pipe_ctx *pipe) in is_master_pipe_for_link()
210 struct pipe_ctx *pipes[MAX_PIPES]) in link_get_master_pipes_with_dpms_on()
213 struct pipe_ctx *pipe = NULL; in link_get_master_pipes_with_dpms_on()
217 pipe = &state->res_ctx.pipe_ctx[i]; in link_get_master_pipes_with_dpms_on()
226 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx, in get_ext_hdmi_settings() argument
233 pipe_ctx->stream->ctx->dc_bios->integrated_info; in get_ext_hdmi_settings()
323 static bool write_i2c(struct pipe_ctx *pipe_ctx, in write_i2c() argument
334 cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz; in write_i2c()
342 if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx, in write_i2c()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 87 void dcn401_program_gamut_remap(struct pipe_ctx *pipe_ctx) in dcn401_program_gamut_remap() argument
91 unsigned int mpcc_id = pipe_ctx->plane_res.mpcc_inst; in dcn401_program_gamut_remap()
92 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn401_program_gamut_remap()
95 if (pipe_ctx->plane_state) in dcn401_program_gamut_remap()
96 ASSERT(pipe_ctx->plane_state->mcm_location == MPCC_MOVABLE_CM_LOCATION_BEFORE); in dcn401_program_gamut_remap()
103 if (pipe_ctx->plane_state && in dcn401_program_gamut_remap()
104 pipe_ctx->plane_state->gamut_remap_matrix.enable_remap == true) { in dcn401_program_gamut_remap()
108 pipe_ctx->plane_state->gamut_remap_matrix.matrix[i]; in dcn401_program_gamut_remap()
124 if (pipe_ctx->top_pipe == NULL) { in dcn401_program_gamut_remap()
125 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { in dcn401_program_gamut_remap()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/ |
| H A D | dce110_hwseq.c | 284 dce110_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, in dce110_set_input_transfer_func() argument
287 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; in dce110_set_input_transfer_func()
607 dce110_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, in dce110_set_output_transfer_func() argument
610 struct transform *xfm = pipe_ctx->plane_res.xfm; in dce110_set_output_transfer_func()
631 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx) in dce110_update_info_frame() argument
636 ASSERT(pipe_ctx->stream); in dce110_update_info_frame()
638 if (pipe_ctx->stream_res.stream_enc == NULL) in dce110_update_info_frame()
641 is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal); in dce110_update_info_frame()
642 is_dp = dc_is_dp_signal(pipe_ctx->stream->signal); in dce110_update_info_frame()
648 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( in dce110_update_info_frame()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/ |
| H A D | hw_sequencer.h | 37 struct pipe_ctx;
64 struct pipe_ctx *pipe_ctx; member
75 struct pipe_ctx *pipe_ctx; member
81 struct pipe_ctx *pipe_ctx; member
86 struct pipe_ctx *pipe_ctx; member
91 struct pipe_ctx *pipe_ctx; member
95 struct pipe_ctx *pipe_ctx; member
105 struct pipe_ctx *pipe_ctx; member
109 struct pipe_ctx *pipe_ctx; member
114 struct pipe_ctx *pipe_ctx; member
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
| H A D | dcn10_hwseq.c | 102 void dcn10_wait_for_pipe_update_if_needed(struct dc *dc, struct pipe_ctx *pipe_ctx, bool is_surface… in dcn10_wait_for_pipe_update_if_needed() argument
105 struct dc_stream_state *stream = pipe_ctx->stream; in dcn10_wait_for_pipe_update_if_needed()
111 if (!pipe_ctx->stream || in dcn10_wait_for_pipe_update_if_needed()
112 !pipe_ctx->stream_res.tg || in dcn10_wait_for_pipe_update_if_needed()
113 !pipe_ctx->stream_res.stream_enc) in dcn10_wait_for_pipe_update_if_needed()
116 if (pipe_ctx->prev_odm_pipe && in dcn10_wait_for_pipe_update_if_needed()
117 pipe_ctx->stream) in dcn10_wait_for_pipe_update_if_needed()
120 if (!pipe_ctx->wait_is_required) in dcn10_wait_for_pipe_update_if_needed()
123 struct timing_generator *tg = pipe_ctx->stream_res.tg; in dcn10_wait_for_pipe_update_if_needed()
128 dc->hwss.calc_vupdate_position(dc, pipe_ctx, &vupdate_start, in dcn10_wait_for_pipe_update_if_needed()
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_resource.c | 701 const struct pipe_ctx *pipe_with_clk_src, in is_sharable_clk_src()
702 const struct pipe_ctx *pipe) in is_sharable_clk_src()
733 struct pipe_ctx *pipe_ctx) in resource_find_used_clk_src_for_sharing() argument
738 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx)) in resource_find_used_clk_src_for_sharing()
739 return res_ctx->pipe_ctx[i].clock_source; in resource_find_used_clk_src_for_sharing()
852 struct pipe_ctx *pipe_ctx, in calculate_plane_rec_in_timing_active() argument
916 const struct dc_stream_state *stream = pipe_ctx->stream; in calculate_plane_rec_in_timing_active()
942 struct pipe_ctx *pipe_ctx, in calculate_mpc_slice_in_timing_active() argument
945 const struct dc_stream_state *stream = pipe_ctx->stream; in calculate_mpc_slice_in_timing_active()
946 int mpc_slice_count = resource_get_mpc_slice_count(pipe_ctx); in calculate_mpc_slice_in_timing_active()
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| H A D | dc_surface.c | 74 struct pipe_ctx *pipe_ctx = &dc_state->res_ctx.pipe_ctx[i]; in dc_plane_get_pipe_mask() local
76 if (pipe_ctx->plane_state == plane_state && pipe_ctx->plane_res.hubp) in dc_plane_get_pipe_mask()
77 pipe_mask |= 1 << pipe_ctx->plane_res.hubp->inst; in dc_plane_get_pipe_mask()
134 struct pipe_ctx *pipe_ctx = in dc_plane_get_status() local
135 &dc->current_state->res_ctx.pipe_ctx[i]; in dc_plane_get_status()
137 if (pipe_ctx->plane_state != plane_state) in dc_plane_get_status()
140 if (pipe_ctx->plane_state && flags.bits.address) in dc_plane_get_status()
141 pipe_ctx->plane_state->status.is_flip_pending = false; in dc_plane_get_status()
149 struct pipe_ctx *pipe_ctx = in dc_plane_get_status() local
150 &dc->current_state->res_ctx.pipe_ctx[i]; in dc_plane_get_status()
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| H A D | dc.c | 432 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in set_long_vtotal()
496 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_adjust_vmin_vmax()
538 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_get_last_used_drr_vtotal()
599 struct pipe_ctx *pipe; in dc_stream_forward_crc_window()
604 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_forward_crc_window()
665 struct pipe_ctx *pipe; in dc_stream_forward_multiple_crc_window()
670 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_forward_multiple_crc_window()
715 struct pipe_ctx *pipe; in dc_stream_configure_crc()
789 struct pipe_ctx *pipe = NULL; in dc_stream_get_crc()
795 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_get_crc()
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| H A D | dc_hw_sequencer.c | 319 struct pipe_ctx *pipe_ctx, in get_mpctree_visual_confirm_color() argument
331 struct pipe_ctx *top_pipe = pipe_ctx; in get_mpctree_visual_confirm_color()
340 const struct pipe_ctx *pipe_ctx, in get_surface_visual_confirm_color() argument
345 switch (pipe_ctx->plane_res.scl_data.format) { in get_surface_visual_confirm_color()
349 if (pipe_ctx->plane_state->layer_index > 0) { in get_surface_visual_confirm_color()
359 if (pipe_ctx->plane_state->layer_index > 0) { in get_surface_visual_confirm_color()
378 if (pipe_ctx->plane_state->layer_index > 0) { in get_surface_visual_confirm_color()
390 struct pipe_ctx *pipe_ctx, in get_hdr_visual_confirm_color() argument
397 struct pipe_ctx *top_pipe_ctx = pipe_ctx; in get_hdr_visual_confirm_color()
465 struct pipe_ctx *pipe_ctx, in get_vabc_visual_confirm_color() argument
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| H A D | dc_stream.c | 258 struct pipe_ctx *pipe_to_program = NULL; in program_cursor_attributes()
267 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; in program_cursor_attributes() local
269 if (pipe_ctx->stream != stream) in program_cursor_attributes()
273 pipe_to_program = pipe_ctx; in program_cursor_attributes()
276 dc->hwss.begin_cursor_offload_update(dc, pipe_ctx); in program_cursor_attributes()
284 dc->hwss.set_cursor_attribute(pipe_ctx); in program_cursor_attributes()
286 dc_send_update_cursor_info_to_dmu(pipe_ctx, i); in program_cursor_attributes()
288 dc->hwss.set_cursor_sdr_white_level(pipe_ctx); in program_cursor_attributes()
290 dc->hwss.update_cursor_offload_pipe(dc, pipe_ctx); in program_cursor_attributes()
405 struct pipe_ctx *pipe_to_program = NULL; in program_cursor_position()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/ |
| H A D | dcn201_hwseq.c | 60 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr) in patch_address_for_sbs_tb_stereo() argument
62 struct dc_plane_state *plane_state = pipe_ctx->plane_state; in patch_address_for_sbs_tb_stereo()
63 bool sec_split = pipe_ctx->top_pipe && in patch_address_for_sbs_tb_stereo()
64 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state; in patch_address_for_sbs_tb_stereo()
67 (pipe_ctx->stream->timing.timing_3d_format == in patch_address_for_sbs_tb_stereo()
69 pipe_ctx->stream->timing.timing_3d_format == in patch_address_for_sbs_tb_stereo()
76 if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE && in patch_address_for_sbs_tb_stereo()
136 void dcn201_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx) in dcn201_update_plane_addr() argument
140 struct dc_plane_state *plane_state = pipe_ctx->plane_state; in dcn201_update_plane_addr()
148 addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr); in dcn201_update_plane_addr()
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| H A D | dcn201_hwseq.h | 31 void dcn201_set_dmdata_attributes(struct pipe_ctx *pipe_ctx);
33 void dcn201_unblank_stream(struct pipe_ctx *pipe_ctx,
35 void dcn201_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);
36 …d dcn201_plane_atomic_disconnect(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);
37 void dcn201_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);
38 void dcn201_set_cursor_attribute(struct pipe_ctx *pipe_ctx);
41 struct pipe_ctx *pipe,
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| /linux/drivers/gpu/drm/amd/display/dc/link/hwss/ |
| H A D | link_hwss_hpo_dp.c | 33 void set_hpo_dp_throttled_vcp_size(struct pipe_ctx *pipe_ctx, in set_hpo_dp_throttled_vcp_size() argument
37 pipe_ctx->stream_res.hpo_dp_stream_enc; in set_hpo_dp_throttled_vcp_size()
39 pipe_ctx->link_res.hpo_dp_link_enc; in set_hpo_dp_throttled_vcp_size()
46 void set_hpo_dp_hblank_min_symbol_width(struct pipe_ctx *pipe_ctx, in set_hpo_dp_hblank_min_symbol_width() argument
51 pipe_ctx->stream_res.hpo_dp_stream_enc; in set_hpo_dp_hblank_min_symbol_width()
52 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; in set_hpo_dp_hblank_min_symbol_width()
56 pipe_ctx->stream->link, link_settings); in set_hpo_dp_hblank_min_symbol_width()
74 void setup_hpo_dp_stream_encoder(struct pipe_ctx *pipe_ctx) in setup_hpo_dp_stream_encoder() argument
76 struct hpo_dp_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; in setup_hpo_dp_stream_encoder()
77 struct hpo_dp_link_encoder *link_enc = pipe_ctx->link_res.hpo_dp_link_enc; in setup_hpo_dp_stream_encoder()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn35/ |
| H A D | dcn35_hwseq.c | 327 static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) in update_dsc_on_stream() argument
329 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; in update_dsc_on_stream()
330 struct dc_stream_state *stream = pipe_ctx->stream; in update_dsc_on_stream()
331 struct pipe_ctx *odm_pipe; in update_dsc_on_stream()
337 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) in update_dsc_on_stream()
347 DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx->stream_res.tg->inst); in update_dsc_on_stream()
354 DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx->stream_res.tg->inst); in update_dsc_on_stream()
363 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; in update_dsc_on_stream()
370 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); in update_dsc_on_stream()
371 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { in update_dsc_on_stream()
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| /linux/drivers/gpu/drm/amd/display/dc/inc/ |
| H A D | link_hwss.h | 38 struct pipe_ctx;
49 void (*set_hblank_min_symbol_width)(struct pipe_ctx *pipe_ctx,
52 void (*set_throttled_vcp_size)(struct pipe_ctx *pipe_ctx,
77 void (*setup_stream_encoder)(struct pipe_ctx *pipe_ctx);
78 void (*reset_stream_encoder)(struct pipe_ctx *pipe_ctx);
79 void (*setup_stream_attribute)(struct pipe_ctx *pipe_ctx);
83 void (*setup_audio_output)(struct pipe_ctx *pipe_ctx,
85 void (*enable_audio_packet)(struct pipe_ctx *pipe_ctx);
86 void (*disable_audio_packet)(struct pipe_ctx *pipe_ctx);
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn21/ |
| H A D | dcn21_hwseq.c | 128 void dcn21_PLAT_58856_wa(struct dc_state *context, struct pipe_ctx *pipe_ctx) in dcn21_PLAT_58856_wa() argument
130 if (!pipe_ctx->stream->dpms_off) in dcn21_PLAT_58856_wa()
133 pipe_ctx->stream->dpms_off = false; in dcn21_PLAT_58856_wa()
134 pipe_ctx->stream->ctx->dc->link_srv->set_dpms_on(context, pipe_ctx); in dcn21_PLAT_58856_wa()
135 pipe_ctx->stream->ctx->dc->link_srv->set_dpms_off(pipe_ctx); in dcn21_PLAT_58856_wa()
136 pipe_ctx->stream->dpms_off = true; in dcn21_PLAT_58856_wa()
178 void dcn21_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx) in dcn21_set_abm_immediate_disable() argument
180 struct abm *abm = pipe_ctx->stream_res.abm; in dcn21_set_abm_immediate_disable()
181 uint32_t otg_inst = pipe_ctx->stream_res.tg->inst; in dcn21_set_abm_immediate_disable()
182 struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl; in dcn21_set_abm_immediate_disable()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn32/ |
| H A D | dcn32_hwseq.c | 239 struct pipe_ctx *pipe = &ctx->res_ctx.pipe_ctx[i]; in dcn32_calculate_cab_allocation()
361 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dcn32_commit_subvp_config() local
363 if (pipe_ctx->stream && dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_MAIN) { in dcn32_commit_subvp_config()
382 struct pipe_ctx *top_pipe_to_program, in dcn32_subvp_pipe_control_lock()
388 struct pipe_ctx *pipe; in dcn32_subvp_pipe_control_lock()
392 pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_subvp_pipe_control_lock()
413 pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_subvp_pipe_control_lock()
447 struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream) in dcn32_set_mpc_shaper_3dlut() argument
449 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn32_set_mpc_shaper_3dlut()
450 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn32_set_mpc_shaper_3dlut()
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| H A D | dcn32_hwseq.h | 50 bool dcn32_set_mcm_luts(struct pipe_ctx *pipe_ctx,
54 struct pipe_ctx *pipe_ctx,
58 struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream);
61 struct pipe_ctx *pipe_ctx,
72 void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
74 void dcn32_update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable);
76 unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, uns…
84 struct pipe_ctx *top_pipe_to_program,
89 void dcn32_unblank_stream(struct pipe_ctx *pipe_ctx,
92 bool dcn32_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx);
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn31/ |
| H A D | dcn31_hwseq.c | 376 void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx) in dcn31_update_info_frame() argument
381 ASSERT(pipe_ctx->stream); in dcn31_update_info_frame()
383 if (pipe_ctx->stream_res.stream_enc == NULL) in dcn31_update_info_frame()
386 is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal); in dcn31_update_info_frame()
387 is_dp = dc_is_dp_signal(pipe_ctx->stream->signal); in dcn31_update_info_frame()
393 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( in dcn31_update_info_frame()
394 pipe_ctx->stream_res.stream_enc, in dcn31_update_info_frame()
395 &pipe_ctx->stream_res.encoder_info_frame); in dcn31_update_info_frame()
396 else if (pipe_ctx->stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { in dcn31_update_info_frame()
397 if (pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->update_dp_info_packets_sdp_line_num) in dcn31_update_info_frame()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource_helpers.c | 41 struct pipe_ctx *pipe_ctx, in dcn32_helper_calculate_mall_bytes_for_cursor() argument
44 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn32_helper_calculate_mall_bytes_for_cursor()
48 switch (pipe_ctx->stream->cursor_attributes.color_format) { in dcn32_helper_calculate_mall_bytes_for_cursor()
67 if (pipe_ctx->stream->cursor_position.enable && (ignore_cursor_buf || in dcn32_helper_calculate_mall_bytes_for_cursor()
114 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_merge_pipes_for_subvp()
136 struct pipe_ctx *top_pipe = pipe->top_pipe; in dcn32_merge_pipes_for_subvp()
137 struct pipe_ctx *bottom_pipe = pipe->bottom_pipe; in dcn32_merge_pipes_for_subvp()
159 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_all_pipes_have_stream_and_plane()
176 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_subvp_in_use()
201 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_any_surfaces_rotated()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/ |
| H A D | dcn30_hwseq.c | 235 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) in dcn30_set_blend_lut() argument
237 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_blend_lut()
256 static bool dcn30_set_mpc_shaper_3dlut(struct pipe_ctx *pipe_ctx, in dcn30_set_mpc_shaper_3dlut() argument
259 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_mpc_shaper_3dlut()
260 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn30_set_mpc_shaper_3dlut()
261 struct dc *dc = pipe_ctx->stream->ctx->dc; in dcn30_set_mpc_shaper_3dlut()
262 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn30_set_mpc_shaper_3dlut()
317 struct pipe_ctx *pipe_ctx, in dcn30_set_input_transfer_func() argument
321 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_input_transfer_func()
346 if (pipe_ctx->stream_res.opp && pipe_ctx->stream_res.opp->ctx) { in dcn30_set_input_transfer_func()
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc_trace.h | 26 #define TRACE_DC_PIPE_STATE(pipe_ctx, index, max_pipes) \ argument
28 struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[index]; \
29 if (pipe_ctx->plane_state) \
30 trace_amdgpu_dm_dc_pipe_state(pipe_ctx->pipe_idx, pipe_ctx->plane_state, \
31 pipe_ctx->stream, &pipe_ctx->plane_res, \
32 pipe_ctx->update_flags.raw); \
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| /linux/drivers/gpu/drm/amd/display/dc/link/protocols/ |
| H A D | link_dp_panel_replay.c | 60 if (dc->current_state->res_ctx.pipe_ctx[i].stream && in dp_pr_set_static_screen_param()
61 dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) { in dp_pr_set_static_screen_param()
62 struct dc_stream_state *stream = dc->current_state->res_ctx.pipe_ctx[i].stream; in dp_pr_set_static_screen_param()
128 if (dc->current_state->res_ctx.pipe_ctx[i].stream in dp_setup_panel_replay()
134 dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg->inst + 1; in dp_setup_panel_replay()
219 if (dc->current_state->res_ctx.pipe_ctx[i].stream && in dp_pr_get_panel_inst()
220 dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) { in dp_pr_get_panel_inst()
222 if (dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg) in dp_pr_get_panel_inst()
223 *inst_out = dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg->inst; in dp_pr_get_panel_inst()
280 struct pipe_ctx *pipe_ctx = NULL; in dp_pr_copy_settings() local
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