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Searched refs:phys_enc (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_encoder_phys_cmd.c41 static void dpu_encoder_phys_cmd_enable_te(struct dpu_encoder_phys *phys_enc);
43 static bool dpu_encoder_phys_cmd_is_master(struct dpu_encoder_phys *phys_enc) in dpu_encoder_phys_cmd_is_master() argument
45 return (phys_enc->split_role != ENC_ROLE_SLAVE); in dpu_encoder_phys_cmd_is_master()
49 struct dpu_encoder_phys *phys_enc) in _dpu_encoder_phys_cmd_update_intf_cfg() argument
52 to_dpu_encoder_phys_cmd(phys_enc); in _dpu_encoder_phys_cmd_update_intf_cfg()
57 ctl = phys_enc->hw_ctl; in _dpu_encoder_phys_cmd_update_intf_cfg()
61 intf_cfg.intf = phys_enc->hw_intf->idx; in _dpu_encoder_phys_cmd_update_intf_cfg()
64 intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); in _dpu_encoder_phys_cmd_update_intf_cfg()
65 intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc); in _dpu_encoder_phys_cmd_update_intf_cfg()
69 if (test_bit(DPU_CTL_ACTIVE_CFG, &ctl->caps->features) && phys_enc->hw_intf->ops.bind_pingpong_blk) in _dpu_encoder_phys_cmd_update_intf_cfg()
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H A Ddpu_encoder_phys_vid.c33 struct dpu_encoder_phys *phys_enc) in dpu_encoder_phys_vid_is_master() argument
37 if (phys_enc->split_role != ENC_ROLE_SLAVE) in dpu_encoder_phys_vid_is_master()
44 const struct dpu_encoder_phys *phys_enc, in drm_mode_to_intf_timing_params() argument
92 if (phys_enc->hw_intf->cap->type == INTF_DSI) { in drm_mode_to_intf_timing_params()
98 if (phys_enc->hw_intf->cap->type == INTF_DP) { in drm_mode_to_intf_timing_params()
105 timing->wide_bus_en = dpu_encoder_is_widebus_enabled(phys_enc->parent); in drm_mode_to_intf_timing_params()
106 timing->compression_en = dpu_encoder_is_dsc_enabled(phys_enc->parent); in drm_mode_to_intf_timing_params()
112 if (phys_enc->hw_intf->cap->type == INTF_DP && timing->wide_bus_en) { in drm_mode_to_intf_timing_params()
125 if (phys_enc->hw_intf->cap->type != INTF_DP && timing->compression_en) { in drm_mode_to_intf_timing_params()
127 dpu_encoder_get_dsc_config(phys_enc->parent); in drm_mode_to_intf_timing_params()
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H A Ddpu_encoder_phys_wb.c32 static bool dpu_encoder_phys_wb_is_master(struct dpu_encoder_phys *phys_enc) in dpu_encoder_phys_wb_is_master() argument
60 struct dpu_encoder_phys *phys_enc) in dpu_encoder_phys_wb_set_ot_limit() argument
62 struct dpu_hw_wb *hw_wb = phys_enc->hw_wb; in dpu_encoder_phys_wb_set_ot_limit()
69 ot_params.width = phys_enc->cached_mode.hdisplay; in dpu_encoder_phys_wb_set_ot_limit()
70 ot_params.height = phys_enc->cached_mode.vdisplay; in dpu_encoder_phys_wb_set_ot_limit()
72 ot_params.frame_rate = drm_mode_vrefresh(&phys_enc->cached_mode); in dpu_encoder_phys_wb_set_ot_limit()
76 if (!_dpu_encoder_phys_wb_clk_force_ctrl(hw_wb, phys_enc->dpu_kms->hw_mdp, in dpu_encoder_phys_wb_set_ot_limit()
80 dpu_vbif_set_ot_limit(phys_enc->dpu_kms, &ot_params); in dpu_encoder_phys_wb_set_ot_limit()
83 _dpu_encoder_phys_wb_clk_force_ctrl(hw_wb, phys_enc->dpu_kms->hw_mdp, in dpu_encoder_phys_wb_set_ot_limit()
92 struct dpu_encoder_phys *phys_enc) in dpu_encoder_phys_wb_set_qos_remap() argument
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H A Ddpu_encoder_phys.h104 int (*wait_for_commit_done)(struct dpu_encoder_phys *phys_enc);
105 int (*wait_for_tx_complete)(struct dpu_encoder_phys *phys_enc);
106 void (*prepare_for_kickoff)(struct dpu_encoder_phys *phys_enc);
107 void (*handle_post_kickoff)(struct dpu_encoder_phys *phys_enc);
108 void (*trigger_start)(struct dpu_encoder_phys *phys_enc);
109 bool (*needs_single_flush)(struct dpu_encoder_phys *phys_enc);
112 void (*prepare_idle_pc)(struct dpu_encoder_phys *phys_enc);
116 void (*prepare_wb_job)(struct dpu_encoder_phys *phys_enc,
118 void (*cleanup_wb_job)(struct dpu_encoder_phys *phys_enc,
120 bool (*is_valid_for_commit)(struct dpu_encoder_phys *phys_enc);
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H A Ddpu_encoder.c220 u32 dpu_encoder_get_drm_fmt(struct dpu_encoder_phys *phys_enc) in dpu_encoder_get_drm_fmt() argument
227 drm_enc = phys_enc->parent; in dpu_encoder_get_drm_fmt()
230 mode = &phys_enc->cached_mode; in dpu_encoder_get_drm_fmt()
238 bool dpu_encoder_needs_periph_flush(struct dpu_encoder_phys *phys_enc) in dpu_encoder_needs_periph_flush() argument
246 drm_enc = phys_enc->parent; in dpu_encoder_needs_periph_flush()
250 mode = &phys_enc->cached_mode; in dpu_encoder_needs_periph_flush()
252 return phys_enc->hw_intf->cap->type == INTF_DP && in dpu_encoder_needs_periph_flush()
388 void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc, in dpu_encoder_helper_report_irq_timeout() argument
392 DRMID(phys_enc->parent), in dpu_encoder_helper_report_irq_timeout()
393 dpu_encoder_helper_get_intf_type(phys_enc->intf_mode), in dpu_encoder_helper_report_irq_timeout()
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