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Searched refs:phydev_dbg (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/net/phy/
H A Dnxp-c45-tja11xx-macsec.c298 phydev_dbg(phydev, "write addr 0x%x value 0x%x\n", addr, value); in nxp_c45_macsec_write()
334 phydev_dbg(phydev, "read addr 0x%x value 0x%x\n", addr, *value); in nxp_c45_macsec_read()
709 phydev_dbg(phydev, "XPN %s\n", phy_secy->secy->xpn ? "on" : "off"); in nxp_c45_tx_sc_update()
715 phydev_dbg(phydev, "key len %u\n", phy_secy->secy->key_len); in nxp_c45_tx_sc_update()
721 phydev_dbg(phydev, "encryption %s\n", in nxp_c45_tx_sc_update()
728 phydev_dbg(phydev, "protect frames %s\n", in nxp_c45_tx_sc_update()
735 phydev_dbg(phydev, "send sci %s\n", in nxp_c45_tx_sc_update()
742 phydev_dbg(phydev, "end station %s\n", in nxp_c45_tx_sc_update()
749 phydev_dbg(phydev, "scb %s\n", in nxp_c45_tx_sc_update()
824 phydev_dbg(phydev, "validate frames %u\n", in nxp_c45_rx_sc_update()
[all …]
H A Dnxp-c45-tja11xx.c1529 phydev_dbg(phydev, "Clause 45 managed PHY abilities 0x%x\n", ret); in nxp_c45_set_phy_mode()
1747 phydev_dbg(phydev, "the phy does not support PTP"); in nxp_c45_probe()
1763 phydev_dbg(phydev, "PTP support not enabled even if the phy supports it"); in nxp_c45_probe()
1775 phydev_dbg(phydev, "MACsec support enabled."); in nxp_c45_probe()
1777 phydev_dbg(phydev, "MACsec support not enabled even if the phy supports it"); in nxp_c45_probe()
H A Dmotorcomm.c2799 phydev_dbg(phydev, in yt8821_read_status()
2805 phydev_dbg(phydev, in yt8821_read_status()
H A Dmicrel.c3918 phydev_dbg(phydev, "successfully registered ptp clock\n"); in lan8814_ptp_probe_once()
/linux/drivers/net/phy/aquantia/
H A Daquantia_firmware.c244 phydev_dbg(phydev, "primary %d IRAM offset=%d size=%d DRAM offset=%d size=%d\n", in aqr_fw_boot()
265 phydev_dbg(phydev, "loading DRAM 0x%08x from offset=%d size=%d\n", in aqr_fw_boot()
272 phydev_dbg(phydev, "loading IRAM 0x%08x from offset=%d size=%d\n", in aqr_fw_boot()